Sunggu Lee

Orcid: 0000-0003-3858-0779

According to our database1, Sunggu Lee authored at least 89 papers between 1990 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
Small-Footprint Convolutional Neural Network with Reduced Feature Map for Voice Activity Detection.
Proceedings of the IEEE International Conference on Acoustics, 2024

2022
Convolutional Neural Networks With Discrete Cosine Transform Features.
IEEE Trans. Computers, 2022

Energy-Efficient Image Processing Using Binary Neural Networks with Hadamard Transform.
Proceedings of the Computer Vision - ACCV 2022, 2022

2021
Layerwise Buffer Voltage Scaling for Energy-Efficient Convolutional Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2020
Hierarchical Approximate Memory for Deep Neural Network Applications.
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020

2019
Memory-Reduced Network Stacking for Edge-Level CNN Architecture With Structured Weight Pruning.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Selective Deep Convolutional Neural Network for Low Cost Distorted Image Classification.
IEEE Access, 2019

Similarity-Based LSTM Architecture for Energy-Efficient Edge-Level Speech Recognition.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Low-Complexity Dynamic Channel Scaling of Noise-Resilient CNN for Intelligent Edge Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

FPGA-Based Sparsity-Aware CNN Accelerator for Noise-Resilient Edge-Level Image Recognition.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

Multi-level Weight Indexing Scheme for Memory-Reduced Convolutional Neural Network.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
Multipliers With Approximate 4-2 Compressors and Error Recovery Modules.
IEEE Embed. Syst. Lett., 2018

Fixed-Point Quantization of 3D Convolutional Neural Networks for Energy-Efficient Action Recognition.
Proceedings of the International SoC Design Conference, 2018

Multi-Mode LSTM Network for Energy-Efficient Speech Recognition.
Proceedings of the International SoC Design Conference, 2018

2017
Accurate Hardware-Efficient Logarithm Circuit.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016
Differential Write-Conscious Software Design on Phase-Change Memory: An SQLite Case Study.
ACM Trans. Design Autom. Electr. Syst., 2016

Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM.
ACM Trans. Design Autom. Electr. Syst., 2016

Memory Access Scheduling for a Smart TV.
IEEE Trans. Circuits Syst. Video Technol., 2016

Iterative Localization of Network Nodes Using Absence of Distance Measurement Information.
Proceedings of the 19th IEEE International Symposium on Real-Time Distributed Computing, 2016

2015
Dynamic Wear Leveling for Phase-Change Memories With Endurance Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Hybrid Main Memory for High Bandwidth Multi-Core System.
IEEE Trans. Multi Scale Comput. Syst., 2015

Extending lifetime of flash memory using strong error correction coding.
IEEE Trans. Consumer Electron., 2015

Time slot assignment for convergecast in wireless sensor networks.
J. Parallel Distributed Comput., 2015

Decentralized task scheduling for a fixed priority multicore embedded RTOS.
Computing, 2015

A small non-volatile write buffer to reduce storage writes in smartphones.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Memory fast-forward: a low cost special function unit to enhance energy efficiency in GPU for big data processing.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
FPGA-based prototyping systems for emerging memory technologies.
Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014

Accelerating graph computation with racetrack memory and pointer-assisted graph representation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Coarse-grained Bubble Razor to exploit the potential of two-phase transparent latch designs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A network congestion-aware memory subsystem for manycore.
ACM Trans. Embed. Comput. Syst., 2013

2012
Optimizing Video Application Design for Phase-Change RAM-Based Main Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Multistep Tag Comparison Method for a Low-Power L2 Cache.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Optimal wake-up scheduling of data gathering trees for wireless sensor networks.
J. Parallel Distributed Comput., 2012

Bloom filter-based dynamic wear leveling for phase-change RAM.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A case study on the application of real phase-change RAM to main memory subsystem.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Write performance improvement by hiding R drift latency in phase-change RAM.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
A novel tag access scheme for low power L2 cache.
Proceedings of the Design, Automation and Test in Europe, 2011

A quantitative analysis of performance benefits of 3D die stacking on mobile and embedded SoC.
Proceedings of the Design, Automation and Test in Europe, 2011

Power management of hybrid DRAM/PRAM-based main memory.
Proceedings of the 48th Design Automation Conference, 2011

Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache.
Proceedings of the 48th Design Automation Conference, 2011

2010
A Network Congestion-Aware Memory Controller.
Proceedings of the NOCS 2010, 2010

2009
Power Modeling of Solid State Disk for Dynamic Power Management Policy Design in Embedded Systems.
Proceedings of the Software Technologies for Embedded and Ubiquitous Systems, 2009

2008
Methods for Increasing Coverage in Wireless Sensor Networks.
Proceedings of the Software Technologies for Embedded and Ubiquitous Systems, 2008

Fast Fault-Tolerant Time Synchronization for Wireless Sensor Networks.
Proceedings of the 11th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2008), 2008

2007
Push-Pull: Deterministic Search-Based DAG Scheduling for Heterogeneous Cluster Systems.
IEEE Trans. Parallel Distributed Syst., 2007

Editorial.
Real Time Syst., 2007

A QoS Routing Protocol for Mobile Ad Hoc Networks Based on a Reservation Pool.
Proceedings of the Software Technologies for Embedded and Ubiquitous Systems, 2007

Data Dissemination for Wireless Sensor Networks.
Proceedings of the Tenth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2007), 2007

2006
A Pseudo-Distance Routing (PDR) Algorithm for Mobile Ad-hoc Networks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

QoS Support for Mobile Ad-Hoc Networks Based on a Reservation Pool.
Proceedings of the Ninth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2006), 2006

A Link Stability Model and Stable Routing for Mobile Ad-Hoc Networks.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

2005
Delay Analysis for Statistical Real-Time Channels in Mobile Ad-Hoc Networks.
Proceedings of the 10th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS 2005), 2005

Push-Pull: Guided Search DAG Scheduling for Heterogeneous Clusters.
Proceedings of the 34th International Conference on Parallel Processing (ICPP 2005), 2005

2004
Design and implementation of a private and public key crypto processor and its application to a security system.
IEEE Trans. Consumer Electron., 2004

Implementation of a TMO-structured real-time airplane-landing simulator on a distributed computing environment.
Softw. Pract. Exp., 2004

2003
Processor Allocation and Task Scheduling of Matrix Chain Products on Parallel Systems.
IEEE Trans. Parallel Distributed Syst., 2003

Task scheduling using a block dependency DAG for block-oriented sparse Cholesky factorization.
Parallel Comput., 2003

Secure checkpointing.
J. Syst. Archit., 2003

Dynamic load balancing for switch-based networks.
J. Parallel Distributed Comput., 2003

Real-time wormhole channels.
J. Parallel Distributed Comput., 2003

2002
Implementation of a TMO-Based Real-Time Airplane Landing Simulator on a Distributed Computing Environment.
Proceedings of the 7th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS 2002), 2002

2001
Measurement and Prediction of Communication Delays in Myrinet Networks.
J. Parallel Distributed Comput., 2001

A Secure Checkpointing System.
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

Path Selection Algorithms for Real-Time Communication.
Proceedings of the Eigth International Conference on Parallel and Distributed Systems, 2001

2000
Path Selection Algorithms for Real-Time Communication.
Int. J. High Speed Comput., 2000

1999
Design and Analysis of the Dual-Torus Network.
New Gener. Comput., 1999

Synchronous Load Balancing in Hypercube Multicomputers with Faulty Nodes.
J. Parallel Distributed Comput., 1999

Path Selection for Real-Time Communication in Wormhole Networks.
Int. J. High Speed Comput., 1999

Reliable Probabilistic Checkpointing.
Proceedings of the 1999 Pacific Rim International Symposium on Dependable Computing (PRDC 1999), 1999

1998
Adaptive Virtual Cut-Through as a Viable Routing Method.
J. Parallel Distributed Comput., 1998

A Real-Time Communication Method for Wormhole Switching Networks.
Proceedings of the 1998 International Conference on Parallel Processing (ICPP '98), 1998

1997
Replicated Process Allocation for Load Distribution in Fault-Tolerant Multicomputers.
IEEE Trans. Computers, 1997

Real-Time Job Scheduling in Hypercube Systems.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

Synchronous Load Balancing in Hypercube Multicomputers with Faulty Nodes.
Proceedings of the 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 1997

Probabilistic Checkpointing.
Proceedings of the Digest of Papers: FTCS-27, 1997

1996
Path Selection for Message Passing in a Circuit-Switched Multicomputer.
J. Parallel Distributed Comput., 1996

1995
Adaptive Virutal Cut-through as an Alternative to Wormhole Routing.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

DTN: A New Partitionable Torus Topology.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

Process Allocation for Load Distribution in Fault-Tolerant Multicomputers.
Proceedings of the Digest of Papers: FTCS-25, 1995

1994
On Probabilistic Diagnosis of Multiprocessor Systems Using Multiple Syndromes.
IEEE Trans. Parallel Distributed Syst., 1994

Interleaved All-to-All Reliable Broadcast on Meshes and Hypercubes.
IEEE Trans. Parallel Distributed Syst., 1994

Probabilistic Diagnosis of Multiprocessor Systems.
ACM Comput. Surv., 1994

Path Selection for Communicating Tasks in a Wormhole-Routed Multicomputer.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

1993
Optimal and Efficient Probabilistic Distributed Diagnosis Schemes.
IEEE Trans. Computers, 1993

1990
Probabilistic multiprocessor and multicomputer diagnosis.
PhD thesis, 1990

Design for test using partial parallel scan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Optimal multiple syndrome probabilistic diagnosis.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990


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