Sungchan Kim

IEEE Trans. Image Process., 2024

2023

Globally-Robust Instance Identification and Locally-Accurate Keypoint Alignment for Multi-Person Pose Estimation.

[BibT_eX]

[DOI]

Fangzheng Tian

Proceedings of the 31st ACM International Conference on Multimedia, 2023

2021

Explaining Neural Networks Using Attentive Knowledge Distillation.

[BibT_eX]

[DOI]

Sensors, 2021

SSPNet: Learning spatiotemporal saliency prediction networks for visual tracking.

[BibT_eX]

[DOI]

Inf. Sci., 2021

Building Reliable Explanations of Unreliable Neural Networks: Locally Smoothing Perspective of Model Interpretation.

[BibT_eX]

[DOI]

Dohun Lim

Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

2020

Special Issue on Information and Communication Technologies for Smart City.

[BibT_eX]

[DOI]

Malay Ranjan Tripathy

Yongchae Jeong

Int. J. Syst. Assur. Eng. Manag., 2020

Salient Explanation for Fine-Grained Classification.

[BibT_eX]

[DOI]

Kanghan Oh

Il-Seok Oh

IEEE Access, 2020

BP-GAN: Interpretable Human Branchpoint Prediction Using Attentive Generative Adversarial Networks.

[BibT_eX]

[DOI]

Sangwoo Yeom

IEEE Access, 2020

2017

An Energy-Aware Runtime Management of Multi-Core Sensory Swarms.

[BibT_eX]

[DOI]

Hoeseok Yang

Sensors, 2017

2016

SoPHy+: Programming model and software platform for hybrid resource management of many-core accelerators.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

In-storage processing of database scans and joins.

[BibT_eX]

[DOI]

Inf. Sci., 2016

LNA topologies for RX carrier aggregation.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

2015

Optimal Checkpoint Selection with Dual-Modular Redundancy Hardening.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

2014

Dynamic Behavior Specification and Dynamic Mapping for Real-Time Embedded Systems: HOPES Approach.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

System-level performance analysis of multiprocessor system-on-chips by combining analytical model and execution time variation.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

SoPHy: A Software Platform for Hybrid Resource Management of Homogeneous Many-core Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES'2015) held on June 13, 2014

Software platform for hybrid resource management of a many-core accelerator for multimedia applications.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

Reliability-aware mapping optimization of multi-core systems with mixed-criticality.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Static Mapping of Mixed-Critical Applications for Fault-Tolerant MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Failure-Aware Task Scheduling of Synchronous Data Flow Graphs Under Real-Time Constraints.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2013

Active disk meets flash: a case for intelligent SSDs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Supercomputing, 2013

Efficient run-time resource management of a manycore accelerator for stream-based applications.

[BibT_eX]

[DOI]

Chanhee Lee

Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

2012

A Parallel Simulation Technique for Multicore Embedded Systems and Its Performance Analysis.

[BibT_eX]

[DOI]

Dukyoung Yun

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Efficient hierarchical bus-matrix architecture exploration of processor pool-based MPSoC.

[BibT_eX]

[DOI]

Young-Pyo Joo

Des. Autom. Embed. Syst., 2012

A cycle-level parallel simulation technique exploiting both space and time parallelism.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

Executing synchronous dataflow graphs on a SPM-based multicore architecture.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Relaxed synchronization technique for speeding-up the parallel simulation of multiprocessor systems.

[BibT_eX]

[DOI]

Dukyoung Yun

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Fast Communication Architecture Exploration of Processor Pool-Based MPSoC via Static Performance Analysis.

[BibT_eX]

[DOI]

Young-Pyo Joo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Fast, Energy Efficient Scan inside Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the International Workshop on Accelerating Data Management Systems Using Modern Processor and Storage Architectures, 2011

Simulation environment configuration for parallel simulation of multicore embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification.

[BibT_eX]

[DOI]

Choonseung Lee

J. Signal Process. Syst., 2010

An MILP-Based Performance Analysis Technique for Non-Preemptive Multitasking MPSoC.

[BibT_eX]

[DOI]

Hoeseok Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A task remapping technique for reliable multi-core embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009

On-chip communication architecture exploration for processor-pool-based MPSoC.

[BibT_eX]

[DOI]

Young-Pyo Joo

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Architecture Exploration of NAND Flash-based Multimedia Card.

[BibT_eX]

[DOI]

Chanik Park

Proceedings of the Design, Automation and Test in Europe, 2008

2007

PeaCE: A hardware-software codesign environment for multimedia embedded systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Compilers, 2007

2006

Efficient exploration of bus-based system-on-chip architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Modeling in Multi-Resolution and Its Applications.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2006

Similarity comparison of mechanical parts to reuse existing designs.

[BibT_eX]

[DOI]

Taesik Hong

Kunwoo Lee

Comput. Aided Des., 2006

History-Based Selective Boolean Operations for Feature-Based Multi-resolution Modeling.

[BibT_eX]

[DOI]

Sang-Hun Lee

Kunwoo Lee

Proceedings of the Computational Science and Its Applications, 2006

2005

Schedule-aware performance estimation of communication architecture for efficient design space exploration.

[BibT_eX]

[DOI]

Chaeseok Im

IEEE Trans. Very Large Scale Integr. Syst., 2005

An integrated approach to realize multi-resolution of B-rep model.

[BibT_eX]

[DOI]

Proceedings of the Tenth ACM Symposium on Solid and Physical Modeling 2005, 2005

2004

Fast design space exploration framework with an efficient performance estimation technique.

[BibT_eX]

[DOI]

Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004

Efficient exploration of on-chip bus architectures and memory allocation.

[BibT_eX]

[DOI]

Chaeseok Im

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2002

Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task Graphs.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

2001

A dataflow specification for system level synthesis of 3D graphics applications.

[BibT_eX]

[DOI]

Chanik Park