Sung-Mo Kang

Orcid: 0000-0001-8424-3410

Affiliations:
  • University of California, Santa Cruz, Department of Electrical and Computer Engineering, CA, USA


According to our database1, Sung-Mo Kang authored at least 23 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Online presence:

On csauthors.net:

Bibliography

2024
A Balanced CMOS Compatible Ternary Memristor-NMOS Logic Family and Its Application.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024

A Memristor Emulation in 180-nm CMOS Process for Spiking Signal Generation and Chaos Application.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

2023
Resistorless Floating/Grounded Memristor Emulator Model With Electronic Tunability.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

A balanced Memristor-CMOS ternary logic family and its application.
CoRR, 2023

Backpropagating Errors Through Memristive Spiking Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Qualitative Approach for the Design of a Locally Active Memristor Based Neuron Circuit.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022
FPGA Synthesis of Ternary Memristor-CMOS Decoders for Active Matrix Microdisplays.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Gradient-Based Neuromorphic Learning on Dynamical RRAM Arrays.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

SPICEprop: Backpropagating Errors Through Memristive Spiking Neural Networks.
CoRR, 2022

A Fully Memristive Spiking Neural Network with Unsupervised Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
High-Density Memristor-CMOS Ternary Logic Family.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

How to Build a Memristive Integrate-and-Fire Model for Spiking Neuronal Signal Generation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

FPGA Synthesis of Ternary Memristor-CMOS Decoders.
CoRR, 2021

CrossStack: A 3-D Reconfigurable RRAM Crossbar Inference Engine.
CoRR, 2021

A 3-D Reconfigurable RRAM Crossbar Inference Engine.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Theoretical Foundations of Memristor Cellular Nonlinear Networks: A DRM<sub>2</sub>-Based Method to Design Memcomputers With Dynamic Memristors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Image Mem-Processing Bio-Inspired Cellular Arrays with Bistable and Analogue Dynamic Memristors.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

2019
Analog Weights in ReRAM DNN Accelerators.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
Formulation and Implementation of Nonlinear Integral Equations to Model Neural Dynamics Within the Vertebrate Retina.
Int. J. Neural Syst., 2018

2017
Maximization of Crossbar Array Memory Using Fundamental Memristor Theory.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2013
Memristor-based neural circuits.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2011
Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines.
IEEE Trans. Very Large Scale Integr. Syst., 2011


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