Sung Kyu Lim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024

Pin-3D: Effective Physical Design Methodology for Multidie Co-Optimization in Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

Heterogeneous Monolithic 3-D IC Designs: Challenges, EDA Solutions, and Power, Performance, Cost Tradeoffs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., March, 2024

A PPA Study for Heterogeneous 3-D IC Options: Monolithic, Hybrid Bonding, and Microbumping.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., March, 2024

GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., March, 2024

Back-side Design Methodology for Power Delivery Network and Clock Routing.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

FastTuner: Transferable Physical Design Parameter Optimization using Fast Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the 2024 International Symposium on Physical Design, 2024

Hetero-3D: Maximizing Performance and Power Delivery Benefits of Heterogeneous 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024

ML-based Physical Design Parameter Optimization for 3D ICs: From Parameter Selection to Optimization.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

GNN-assisted Back-side Clock Routing Methodology for Advance Technologies.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs.

[BibT_eX]

[DOI]

Srivatsa Rangachar Srinivasa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs.

[BibT_eX]

[DOI]

Francisco Muñoz-Martínez

Tanay Karnik

Tushar Krishna

IEEE Trans. Very Large Scale Integr. Syst., October, 2023

GNN-based Multi-bit Flip-flop Clustering and Post-clustering Design Optimization for Energy-efficient 3D ICs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., September, 2023

A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3D vs. True-3D Placers.

[BibT_eX]

[DOI]

Gauthaman Murali

ACM Trans. Design Autom. Electr. Syst., September, 2023

ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., July, 2023

Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials.

[BibT_eX]

[DOI]

Marc González Tallada

Narasinga Rao Miniskar

Int. J. High Perform. Comput. Appl., July, 2023

Parameter Optimization of VLSI Placement Through Deep Reinforcement Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., March, 2023

On Legalization of Die Bonding Bumps and Pads for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2023 International Symposium on Physical Design, 2023

DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning.

[BibT_eX]

[DOI]

Proceedings of the 2023 International Symposium on Physical Design, 2023

A Comparative Study on Front-Side, Buried and Back-Side Power Rail Topologies in 3nm Technology Node.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

A 3D Implementation of Convolutional Neural Network for Fast Inference.

[BibT_eX]

[DOI]

Narasinga Rao Miniskar

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3D DNN Accelerators.

[BibT_eX]

[DOI]

Gauthaman Murali

Aditya Iyer

Navneeth Ravichandran

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Securing Heterogeneous 2.5D ICs Against IP Theft through Dynamic Interposer Obfuscation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

INVITED: Design Automation Needs for Monolithic 3D ICs: Accomplishments and Gaps.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits.

[BibT_eX]

[DOI]

Pruek Vanna-Iampikul

Mohanalingam Kathaperumal

Serhat Erdogan

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Metal Layer Sharing: A Routing Optimization Technique for Monolithic 3D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Clock Tree Prediction and Optimization Framework Using Generative Adversarial Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Design Automation and Test Solutions for Monolithic 3D ICs.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

Unsupervised Digit Recognition Using Cosine Similarity In A Neuromemristive Competitive Learning System.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Placement Optimization via PPA-Directed Graph Clustering.

[BibT_eX]

[DOI]

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

Driving Early Physical Synthesis Exploration through End-of-Flow Total Power Prediction.

[BibT_eX]

[DOI]

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

Routing Layer Sharing: A New Opportunity for Routing Optimization in Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs.

[BibT_eX]

[DOI]

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs.

[BibT_eX]

[DOI]

Matheus A. Cavalcante

Samuel Riedel

Luca Benini

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

On Advancing Physical Design Using Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration.

[BibT_eX]

[DOI]

Matheus A. Cavalcante

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors.

[BibT_eX]

[DOI]

Lennart Bamberg

IEEE Trans. Very Large Scale Integr. Syst., 2021

Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems.

[BibT_eX]

[DOI]

Majid Ahadi Dolatsara

Madhavan Swaminathan

Tushar Krishna

IEEE Trans. Very Large Scale Integr. Syst., 2021

Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs.

[BibT_eX]

[DOI]

Shao-Chun Hung

IEEE Trans. Very Large Scale Integr. Syst., 2021

Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2021

Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Automatic Generation of Translators for Packet-Based and Emerging Protocols.

[BibT_eX]

[DOI]

Brian Crafton

Arijit Raychowdhury

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Physical Design Challenges and Solutions for Emerging Heterogeneous 3D Integration Technologies.

[BibT_eX]

[DOI]

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

ML-Based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip Optimization.

[BibT_eX]

[DOI]

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

The Law of Attraction: Affinity-Aware Placement Optimization using Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Security Closure of Physical Layouts ICCAD Special Session Paper.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Heterogeneous 3D ICs: Current Status and Future Directions for Physical Design Technologies.

[BibT_eX]

[DOI]

Gauthaman Murali

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Heterogeneous Monolithic 3D ICs: EDA Solutions, and Power, Performance, Cost Tradeoffs.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Micro-bumping, Hybrid Bonding, or Monolithic? A PPA Study for Heterogeneous 3D IC Options.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

A COTS-Based Novel 3-D DRAM Memory Cube Architecture for Space Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Improving FPGA-Based Logic Emulation Systems through Machine Learning.

[BibT_eX]

[DOI]

Etienne Lepercq

Jose Escobedo Del Cid

ACM Trans. Design Autom. Electr. Syst., 2020

Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Advances in Design and Test of Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Des. Test, 2020

Vortex: OpenCL Compatible RISC-V GPGPU.

[BibT_eX]

[DOI]

CoRR, 2020

Heterogeneous 3D Integration for a RISC-V System With STT-MRAM.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2020

Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Design Trends, 2020

Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics.

[BibT_eX]

[DOI]

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Pin-in-the-middle: an efficient block pin assignment methodology for block-level monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet Integration.

[BibT_eX]

[DOI]

Jinwoo Kim

Nael Mizanur Rahman

Majid Ahadi Dolatsara

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

A Fault-Tolerant and High-Speed Memory Controller Targeting 3D Flash Memory Cubes for Space Applications.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

A Fast Learning-Driven Signoff Power Optimization Framework.

[BibT_eX]

[DOI]

Siddhartha Nath

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

RTL-to-GDS Design Tools for Monolithic 3D ICs.

[BibT_eX]

[DOI]

Saibal Mukhopadhyay

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

VLSI Placement Parameter Optimization using Deep Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs.

[BibT_eX]

[DOI]

Kambiz Samadi

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs <sup>*</sup>.

[BibT_eX]

[DOI]

Shao-Chun Hung

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Entropy Production-Based Full-Chip Fatigue Analysis: From Theory to Mobile Applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Logic-on-Memory Processor-System Design With Monolithic 3-D Technology.

[BibT_eX]

[DOI]

IEEE Micro, 2019

Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded Inductors.

[BibT_eX]

[DOI]

Hakki Mert Torun

Huan Yu

Nihar Dasari

Proceedings of the International Conference on Computer-Aided Design, 2019

GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Reducing Compilation Effort in Commercial FPGA Emulation Systems Using Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Logic Monolithic 3D ICs: PPA Benefits and EDA Tools Necessary.

[BibT_eX]

[DOI]

Da Eun Shim

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE European Test Symposium, 2019

RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2018

A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems.

[BibT_eX]

[DOI]

Md Musabbir Adnan

Sagarvarma Sayyaparaju

Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on Physical Design, 2018

Road to High-Performance 3D ICs: Performance Optimization Methodologies for Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Area-efficient and low-power face-to-face-bonded 3D liquid state machine design.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

In-growth test for monolithic 3D integrated SRAM.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Design and architectural co-optimization of monolithic 3D liquid state machine-based neuromorphic processor.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

A novel 3D DRAM memory cube architecture for space applications.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

TSV-Based 3-D ICs: Design Methods and Tools.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors.

[BibT_eX]

[DOI]

Sensors, 2017

Bringing 3D ICs to Aerospace: Needs for Design Tools and Methodologies.

[BibT_eX]

[DOI]

J. Inform. and Commun. Convergence Engineering, 2017

Improving Performance under Process and Voltage Variations in Near-Threshold Computing Using 3D ICs.

[BibT_eX]

[DOI]

Sandeep Kumar Samal

Guoqing Chen

ACM J. Emerg. Technol. Comput. Syst., 2017

Evaluating online-learning in memristive neuromorphic circuits.

[BibT_eX]

[DOI]

Proceedings of the Neuromorphic Computing Symposium, 2017

Full chip power benefits with negative capacitance FETs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Frequency and time domain analysis of power delivery network for monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library: (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper).

[BibT_eX]

[DOI]

Abhishek Koneru

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Design and Analysis of a Stochastic Flash Analog-to-Digital Converter in 3D IC technology for integration with ultrasound transducer array.

[BibT_eX]

[DOI]

Hourieh Attarzadeh

Trond Ytterdal

Microelectron. J., 2016

Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

Device Coupling Effects of Monolithic 3D Inverters.

[BibT_eX]

[DOI]

Yun Seop Yu

J. Inform. and Commun. Convergence Engineering, 2016

Machine Learning Based Variation Modeling and Optimization for 3D ICs.

[BibT_eX]

[DOI]

Sandeep Kumar Samal

Guoqing Chen

Lalinthip Tangjittaweechai

J. Inform. and Commun. Convergence Engineering, 2016

Fast bidirectional shortest path on GPU.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools - Part 2.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Monolithic 3D IC design: Power, performance, and area impact at 7nm.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Match-making for monolithic 3D IC: finding the right technology node.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Scan Test of Die Logic in 3-D ICs Using TSV Probing.

[BibT_eX]

[DOI]

Brandon Noia

IEEE Trans. Very Large Scale Integr. Syst., 2015

Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling.

[BibT_eX]

[DOI]

Yarui Peng

Dusan Petranovic

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory).

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits.

[BibT_eX]

[DOI]

Taigon Song

J. Inform. and Commun. Convergence Engineering, 2015

Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs.

[BibT_eX]

[DOI]

Taigon Song

J. Inform. and Commun. Convergence Engineering, 2015

Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities.

[BibT_eX]

[DOI]

IEEE Des. Test, 2015

Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools.

[BibT_eX]

[DOI]

IEEE Des. Test, 2015

On diagnosable and tunable 3D clock network design for lifetime reliability enhancement.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

Power benefit study of monolithic 3D IC at the 7nm technology node.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Stacking integration methodologies in 3D IC for 3D ultrasound image processing application: A stochastic flash ADC design case study.

[BibT_eX]

[DOI]

Hourieh Attarzadeh

Trond Ytterdal

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A Novel Entropy Production Based Full-Chip TSV Fatigue Analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding Selection.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Low Power Monolithic 3D IC Design of Asynchronous AES Core.

[BibT_eX]

[DOI]

Neela Lohith Penmetsa

Christos P. Sotiriou

Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014

Backend Dielectric Reliability Full Chip Simulator.

[BibT_eX]

[DOI]

Muhammad Muqarrab Bashir

IEEE Trans. Very Large Scale Integr. Syst., 2014

Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Electromigration Study for Multiscale Power/Ground Vias in TSV-Based 3-D ICs.

[BibT_eX]

[DOI]

Jiwoo Pak

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs.

[BibT_eX]

[DOI]

Saibal Mukhopadhyay

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Simulation of system backend dielectric reliability.

[BibT_eX]

[DOI]

Microelectron. J., 2014

Design Challenges and Solutions for Ultra-High-Density Monolithic 3D ICs.

[BibT_eX]

[DOI]

J. Inform. and Commun. Convergence Engineering, 2014

Research Needs for TSV-Based 3D IC Architectural Floorplanning.

[BibT_eX]

[DOI]

J. Inform. and Commun. Convergence Engineering, 2014

TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC.

[BibT_eX]

[DOI]

Commun. ACM, 2014

Design and CAD methodologies for low power gate-level monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Full chip impact study of power delivery network designs in monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

On GPU bus power reduction with 3D IC technologies.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling.

[BibT_eX]

[DOI]

Yarui Peng

Dusan Petranovic

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures.

[BibT_eX]

[DOI]

Junghee Lee

Chrysostomos Nicopoulos

IEEE Trans. Very Large Scale Integr. Syst., 2013

Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Ultrahigh Density Logic Designs Using Monolithic 3-D Integration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations.

[BibT_eX]

[DOI]

Moongon Jung

Sai Manoj Pudukotai Dinakarrao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical-Thermal-Mechanical Coupling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Design and analysis of 3D IC-based low power stereo matching processors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Novel crack sensor for TSV-based 3D integrated circuits: design and deployment perspectives.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs.

[BibT_eX]

[DOI]

Jiwoo Pak

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Power benefit study for ultra-high density transistor-level monolithic 3D ICs.

[BibT_eX]

[DOI]

Daniel B. Limbrick

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

High-density integration of functional modules using monolithic 3D-IC technology.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Test-TSV estimation during 3D-IC partitioning.

[BibT_eX]

[DOI]

Kambiz Samadi

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

Distributed TSV Topology for 3-D Power-Supply Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Backend dielectric reliability simulator for microprocessor system.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2012

Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Transition delay fault testing of 3D ICs with IR-drop study.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Scan test of die logic in 3D ICs using TSV probing.

[BibT_eX]

[DOI]

Brandon Noia

Proceedings of the 2012 IEEE International Test Conference, 2012

3D-MAPS: 3D Massively parallel processor with stacked memory.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices.

[BibT_eX]

[DOI]

Kaiyuan Yang

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A design tradeoff study with monolithic 3D integration.

[BibT_eX]

[DOI]

Chang Liu

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Fast delay estimation with buffer insertion for through-silicon-via-based 3D interconnects.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

TSV array utilization in low-power 3D clock network design.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Electromigration-aware routing for 3D ICs with stress-aware EM modeling.

[BibT_eX]

[DOI]

Jiwoo Pak

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Ultra high density logic designs using transistor-level monolithic 3D integration.

[BibT_eX]

[DOI]

Patrick Morrow

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs.

[BibT_eX]

[DOI]

Michael Scheuermann

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs.

[BibT_eX]

[DOI]

Moongon Jung

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Exploiting die-to-die thermal coupling in 3D IC placement.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Slew-aware buffer insertion for through-silicon-via-based 3D ICs.

[BibT_eX]

[DOI]

Inki Hong

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

TSV Stress-Aware ATPG for 3D Stacked ICs.

[BibT_eX]

[DOI]

Sergej Deutsch

Proceedings of the 21st IEEE Asian Test Symposium, 2012

Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Design for manufacturability and reliability for TSV-based 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Block-level 3D IC design with through-silicon-via planning.

[BibT_eX]

[DOI]

Rasit Onur Topaloglu

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2011

Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Co-Optimization and Analysis of Signal, Power, and Thermal Interconnects in 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Impact of irregular geometries on low-k dielectric breakdown.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2011

Scan chain and power delivery network synthesis for pre-bond test of 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs.

[BibT_eX]

[DOI]

Suyoun Kim

Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Signal integrity analysis and optimization for 3D ICs.

[BibT_eX]

[DOI]

Chang Liu

Taigon Song

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Power-supply-network design in 3D integrated systems.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

TSV density-driven global placement for 3D stacked ICs.

[BibT_eX]

[DOI]

Rasit Onur Topaloglu

Proceedings of the International SoC Design Conference, 2011

Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A novel TSV topology for many-tier 3D power-delivery networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2010

SONOS-Type Flash Memory with HfO<sub>2</sub> Thinner than 4 nm as Trapping Layer Using Atomic Layer Deposition.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2010

Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Through-silicon-via management during 3D physical design: When to add and how many?

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Stress-driven 3D-IC placement with TSV keep-out zone and regularity study.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

TSV stress aware timing analysis with applications to 3D-IC layout optimization.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Buffered clock tree sizing for skew minimization under power and thermal budgets.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Timing analysis and optimization for 3D stacked multi-core microprocessors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on 3D System Integration, 2010

A study of IR-drop noise issues in 3D ICs with through-silicon-vias.

[BibT_eX]

[DOI]

Moongon Jung

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing.

[BibT_eX]

[DOI]

I. Faik Baskaya

David V. Anderson

IEEE Trans. Circuits Syst. II Express Briefs, 2009

Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs.

[BibT_eX]

[DOI]

Saibal Mukhopadhyay

Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

Slew-aware clock tree design for reliable subthreshold circuits.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Pre-bond testable low-power clock tree design for 3D stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs.

[BibT_eX]

[DOI]

Rohan Goel

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A study of Through-Silicon-Via impact on the 3D stacked IC layout.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A generic reconfigurable array specification and programming environment (GRASPER).

[BibT_eX]

[DOI]

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Decoupling capacitor planning with analytical delay model on RLC power grid.

[BibT_eX]

[DOI]

Ye Tao

Proceedings of the Design, Automation and Test in Europe, 2009

Co-design of signal, power, and thermal distribution networks for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Thermal optimization in multi-granularity multi-core floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Global bus route optimization with application to microarchitectural design exploration.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

Buffered clock tree synthesis for 3D ICs under thermal variations.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Bus-aware microarchitectural floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

A unified methodology for power supply noise reduction in modern microarchitecture design.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Introduction to special issue on demonstrable software systems and hardware platforms.

[BibT_eX]

[DOI]

Massoud Pedram

ACM Trans. Design Autom. Electr. Syst., 2007

Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs.

[BibT_eX]

[DOI]

Mario Vittes

Chinnakrishnan S. Ballapuram

Hsien-Hsin S. Lee

Gabriel H. Loh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Whitespace redistribution for thermal via insertion in 3D stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

Placement and routing of RF embedded passive designs in LCP substrate.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

Thermal-aware Steiner routing for 3D stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

An Efficient Computation of Statistically Critical Sequential Paths Under Retiming.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Multi-Objective Module Placement For 3-D System-On-Package.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Placement for large-scale floating-gate field-programable analog arrays.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Traffic: a novel geometric algorithm for fast wire-optimized floorplanning.

[BibT_eX]

[DOI]

Peter G. Sassone

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Block-level 3-D Global Routing With an Application to 3-D Packaging.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Profile-guided microarchitectural floor planning for deep submicron processor design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Profile-Driven Instruction Mapping for Dataflow Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design.

[BibT_eX]

[DOI]

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

3D floorplanning with thermal vias.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Optical routing for 3D system-on-package.

[BibT_eX]

[DOI]

Somaskanda Thyagaraja

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Microarchitectural floorplanning under performance and thermal tradeoff.

[BibT_eX]

[DOI]

Mario Vittes

Chinnakrishnan S. Ballapuram

Hsien-Hsin S. Lee

Gabriel H. Loh

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Statistical Bellman-Ford algorithm with an application to retiming.

[BibT_eX]

[DOI]

Thaisiri Watewai

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Partitioning and placement for buildable QCA circuits.

[BibT_eX]

[DOI]

Michael T. Niemier

ACM J. Emerg. Technol. Comput. Syst., 2005

Automatic cell placement for quantum-dot cellular automata.

[BibT_eX]

[DOI]

Michael T. Niemier

Integr., 2005

Physical Design for 3D System on Package.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2005

Reliability-aware floorplanning for 3D circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Mapping algorithm for large-scale field programmable analog array.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Physical Design, 2005

Wire-driven microarchitectural design space exploration.

[BibT_eX]

[DOI]

Chinnakrishnan S. Ballapuram

Hsien-Hsin S. Lee

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

QCA channel routing with wire crossing minimization.

[BibT_eX]

[DOI]

Brian Stephen Smith

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

3D module placement for congestion and power noise reduction.

[BibT_eX]

[DOI]

Cheng-Kok Koh

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

MILP-based Placement and Routing for Dataflow Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Hierarchical Placement for Large-scale FPAA.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Placement for configurable dataflow architecture.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Wire congestion and thermal aware 3D global placement.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Retiming-based timing analysis with an application to mincut-based global placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Edge separability-based circuit clustering with application to multilevel circuit partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Multi-layer floorplanning for reliable system-on-package.

[BibT_eX]

Pun Hang Shiu

Siddharth Easwar

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Simultaneous delay and power optimization in global placement.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Automatic cell placement for quantum-dot cellular automata.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Net and Pin Distribution for 3D Package Global Routing.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Profile-guided microarchitectural floorplanning for deep submicron processor design.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Layer assignment for reliable system-on-package.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Performance-driven global placement via adaptive network characterization.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning.

[BibT_eX]

[DOI]

Peter G. Sassone

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2000

Physical Planning with Retiming.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Performance driven multi-level and multiway partitioning with retiming.

[BibT_eX]

[DOI]

Chang Wu

Proceedings of the 37th Conference on Design Automation, 2000

Multi-way partitioning using bi-partition heuristics.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

Performance driven multiway partitioning.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

Edge separability based circuit clustering with application to circuit partitioning.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1998

Multiway partitioning with pairwise movement.

[BibT_eX]

[DOI]