Sung Kim
Orcid: 0000-0002-9010-4617
According to our database1,
Sung Kim
authored at least 50 papers
between 2000 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2018, "For contributions to the design of microfabricated neural prosthetic devices".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
2022
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory.
IEEE J. Solid State Circuits, 2022
2021
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the 18th International Conference on Security and Cryptography, 2021
2020
Proceedings of the CODASPY '20: Tenth ACM Conference on Data and Application Security and Privacy, 2020
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020
2019
An All-Digital Fused PLL-Buck Architecture for 82% Average V<sub>dd</sub>-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor.
IEEE J. Solid State Circuits, 2019
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains.
IEEE J. Solid State Circuits, 2019
2018
Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Scientometrics, 2018
Novel approaches for bioinformatic analysis of salivary RNA sequencing data for development.
Bioinform., 2018
An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
0.5V-VIN, 165-MA/MM<sup>2</sup> Fully-Integrated Digital LDO Based on Event-Driven Self-Trisuerina Control.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Demo/poster abstract: Enabling time-critical applications over next-generation 802.11 networks.
Proceedings of the IEEE INFOCOM 2018, 2018
A 0.78-µW 96-Ch. Deep Sub-Vt Neural Spike Processor Integrated with a Nanowatt Power Management Unit.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Actual Privacy Self-Disclosure on Online Social Network sites: Reflective-impulsive Model.
Proceedings of the 26th European Conference on Information Systems: Beyond Digitization, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 24th Americas Conference on Information Systems, 2018
2017
IEEE Trans. Intell. Transp. Syst., 2017
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017
2015
Information Technology Research in the Academy: Insights from Theses and Dissertations.
Proceedings of the 4th Annual ACM Conference on Research in Information Technology, 2015
Proceedings of the IEEE First International Smart Cities Conference, 2015
2014
2011
EURASIP J. Wirel. Commun. Netw., 2011
Linked statistical shape models for multi-modal segmentation: application to prostate CT-MR segmentation in radiotherapy planning.
Proceedings of the Medical Imaging 2011: Computer-Aided Diagnosis, 2011
Proceedings of the International Conference on Information Systems, 2011
2010
Proceedings of the 2010 IEEE International Conference on Bioinformatics and Biomedicine Workshops, 2010
2009
Improved Multiuser MIMO Unitary Precoding Using Partial Channel State Information and Insights from the Riemannian Manifold.
IEEE Trans. Wirel. Commun., 2009
2008
IEEE Trans. Consumer Electron., 2008
2006
Int. J. Netw. Manag., 2006
Application of AI Planning Technique in Software Engineering.
Proceedings of the 15th International Conference on Software Engineering and Data Engineering (SEDE-2006), 2006
A Point-to-Point Protocol Improvement to Reduce Data Call Setup Latency in Cdma2000 System.
Proceedings of the NETWORKING 2006, 2006
Proceedings of the 30th Annual International Computer Software and Applications Conference, 2006
2005
Proceedings of the Advances in Multimedia Information Processing, 2005
Proceedings of the Digital Libraries: Implementing Strategies and Sharing Experiences, 2005
2004
Circuit and microarchitectural techniques for processor on -chip cache leakage power reduction.
PhD thesis, 2004
Systematic Reliability Analysis of a Class of Application-Specific Embedded Software Frameworks.
IEEE Trans. Software Eng., 2004
2003
Critical Success Factors for is Outsourcing Implementation from an Interorganizational Relationship Perspective.
J. Comput. Inf. Syst., 2003
Proceedings of the 14th International Symposium on Software Reliability Engineering (ISSRE 2003), 2003
Performance Comparison between TCP-Reno and Freeze-Snoop TCP/SACK over cdma2000 Network Environments.
Proceedings of the High Speed Networks and Multimedia Communications, 2003
2002
Proceedings of the 13th International Symposium on Software Reliability Engineering (ISSRE 2002), 2002
An Architecture-Based Comparison of Verification and Statistical Reliability Assessment Methods for Embedded Software Systems.
Proceedings of the 5th International Symposiun on Object Oriented Real-Time Distributed Computing, 2002
Proceedings of the Mobile Communications, 7th CDMA International Conference, CIC 2002, Seoul, Korea, October 29, 2002
2001
Proceedings of the Fifth Pacific Asia Conference on Information Systems, 2001
Reliability of Systems of Independently Developable End-User Assessable Logical (IDEAL) Programs.
Proceedings of the 12th International Symposium on Software Reliability Engineering (ISSRE 2001), 2001
Proceedings of the 6th IEEE International Symposium on High-Assurance Systems Engineering (HASE 2001), 2001
2000
Validation of the End-User Computing Satisfaction Instrument in Case Tool Environments.
J. Comput. Inf. Syst., 2000