A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM. - Jong-Chern Lee; Sin-Hyun Jin; Dae-Suk Kim; Young Jun Ku; Chul Kim; Byung-Kwon Park; Hong-Gyeom Kim; Seong-Jun Ahn; Jaejin Lee; Sung-Joo Hong (A-SSCC, 2011)

25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV. - Dong-Uk Lee; Kyung Whan Kim; Kwan-Weon Kim; Hongjung Kim; Ju Young Kim; Young Jun Park; Jae Hwan Kim; Dae Suk Kim; Heat Bit Park; Jin Wook Shin; Jang Hwan Cho; Ki Hun Kwon; et al. (ISSCC, 2014)

25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. - Hyun-Woo Lee; Junyoung Song; Sangah Hyun; Seunggeun Baek; Yuri Lim; Jungwan Lee; Minsu Park; Haerang Choi; Changkyu Choi; Jin-Youp Cha; Jaeil Kim; Hoon Choi; et al. (ISSCC, 2014)

An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM. - Dong-Uk Lee; Kyung Whan Kim; Kwan-Weon Kim; Kang Seol Lee; Sang Jin Byeon; Jin-Hee Cho; Han Ho Jin; Sang Kyun Nam; Jaejin Lee; Jun Hyun Chun; Sung-Joo Hong (VLSIC, 2014)