Sung-En Hsieh

According to our database, Sung-En Hsieh authored at least 13 papers between 2015 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

A 70.85-86.27TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation.

Sung-En Hsieh, Chun-Hao Wei, Cheng-Xin Xue, Hung-Wei Lin, Wei-Hsuan Tu, En-Jui Chang, Kai-Taing Yang, Po-Heng Chen, Wei-Nan Liao, Li Lian Low, Chia-Da Lee, Allen-Cl Lu, Jenwei Liang, Chih-Chung Cheng, Tzung-Hung Kang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 1.8GHz 12b Pre-Sampling Pipelined ADC with Reference Buffer and OP Power Relaxations.

Sung-En Hsieh, Tzu-Chien Wu, Chun-Chih Hou

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2019

A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator.

Sung-En Hsieh, Chih-Cheng Hsieh

IEEE J. Solid State Circuits, 2019

2018

A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization.

Sung-En Hsieh, Chen-Che Kao, Chih-Cheng Hsieh

IEEE J. Solid State Circuits, 2018

A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC.

Sung-En Hsieh, Chih-Cheng Hsieh

IEEE J. Solid State Circuits, 2018

A 0.4V 13b 270kS/S SAR-ISDM ADC with an opamp-less time-domain integrator.

Sung-En Hsieh, Chih-Cheng Hsieh

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interference Rejections.

Hsiang-Lin Chen, Sung-En Hsieh, Tzu-Hsiang Hsu, Chih-Cheng Hsieh

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017

A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization.

Chen-Che Kao, Sung-En Hsieh, Chih-Cheng Hsieh

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016

A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS.

Sung-En Hsieh, Chih-Cheng Hsieh

IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC.

Sung-En Hsieh, Chih-Cheng Hsieh

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 0.3V 0.705fJ/conversion-step 10-bit SAR ADC with shifted monotonie switching scheme in 90nm CMOS.

Sung-En Hsieh, Chih-Cheng Hsieh

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An integrated CMOS optical sensing chip for multiple bio-signal detections.

Albert Yen-Chih Chiou, Sung-En Hsieh, Yan-Quan Pan, Chia-Chi Kuo, Chih-Cheng Hsieh

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

A 1.2V 1MS/s 7.65fJ/conversion-step 12-bit hybrid SAR ADC with time-to-digital converter.

Sung-En Hsieh, Cheng-Kang Ho, Chih-Cheng Hsieh

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015