Sun ik Heo
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Bibliography
2019
Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Diffusion break-aware leakage power optimization and detailed placement in sub-10nm VLSI.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019