Sumitha George
Orcid: 0000-0002-5924-8807
According to our database1,
Sumitha George
authored at least 31 papers
between 2016 and 2024.
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Bibliography
2024
ACM Trans. Design Autom. Electr. Syst., March, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
FAST: A Fully-Concurrent Access SRAM Topology for High Row-Wise Parallelism Applications Based on Dynamic Shift Operations.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023
CoRR, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
WeightLock: A Mixed-Grained Weight Encryption Approach Using Local Decrypting Units for Ciphertext Computing in DNN Accelerators.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Ferroelectric FET based Context-Switching FPGA Enabling Dynamic Reconfiguration for Adaptive Deep Learning Machines.
CoRR, 2022
ALL-MASK: A Reconfigurable Logic Locking Method for Multicore Architecture with Sequential-Instruction-Oriented Key.
CoRR, 2022
FAST: A Fully-Concurrent Access Technique to All SRAM Rows for Enhanced Speed and Energy Efficiency in Data-Intensive Applications.
CoRR, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
An 8T/Cell FeFET-Based Nonvolatile SRAM with Improved Density and Sub-fJ Backup and Restore Energy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2021
Capacitive Content-Addressable Memory: A Highly Reliable and Scalable Approach to Energy-Efficient Parallel Pattern Matching Applications.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
2020
Optimization of Intercache Traffic Entanglement in Tagless Caches With Tiling Opportunities.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
2019
IEEE Des. Test, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
2016
Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016