Sumio Morioka

According to our database, Sumio Morioka authored at least 25 papers between 1994 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Feasibility Study with Actual Space Rockets Towards Information Theoretically Secure Radio Communication.

Sumio Morioka, Satoshi Obana, Maki Yoshida

Proceedings of the Intelligent Computing, 2024

2023

Secure Communication via GNSS-based Key Synchronization.

Maki Yoshida, Sumio Morioka, Satoshi Obana

Proceedings of Work-in-Progress in Hardware and Software for Location Computation (WIPHAL 2023), 2023

2022

On Cryptographic Algorithms and Key Length for Delayed Disclosure Authentication of GNSS.

Maki Yoshida, Sumio Morioka, Satoshi Obana

Proceedings of the 2022 International Conference on Localization and GNSS, 2022

2021

A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware.

Rei Ueno, Naofumi Homma, Sumio Morioka, Takafumi Aoki

IEEE Des. Test, 2021

2020

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression.

Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger

IEEE Trans. Computers, 2020

Tweakable TWINE: Building a Tweakable Block Cipher on Generalized Feistel Structure.

Kosei Sakamoto, Kazuhiko Minematsu, Nao Shibata, Maki Shigeri, Hiroyasu Kubo, Yuki Funabiki, Andrey Bogdanov, Sumio Morioka, Takanori Isobe

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

2017

Hierarchical Formal Verification Combining Algebraic Transformation with PPRM Expansion and Its Application to Masked Cryptographic Processors.

Rei Ueno, Naofumi Homma, Takafumi Aoki, Sumio Morioka

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Automatic generation of formally-proven tamper-resistant Galois-field multipliers based on generalized masking scheme.

Rei Ueno, Naofumi Homma, Sumio Morioka, Takafumi Aoki

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation.

Rei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki

IACR Cryptol. ePrint Arch., 2016

2014

CLOC: Authenticated Encryption for Short Input.

Tetsu Iwata, Kazuhiko Minematsu, Jian Guo, Sumio Morioka

IACR Cryptol. ePrint Arch., 2014

A hierarchical formal approach to verifying side-channel resistant cryptographic processors.

Kotaro Okamoto, Naofumi Homma, Takafumi Aoki, Sumio Morioka

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

2012

$\textnormal{\textsc{TWINE}}$ : A Lightweight Block Cipher for Multiple Platforms.

Tomoyasu Suzaki, Kazuhiko Minematsu, Sumio Morioka, Eita Kobayashi

Proceedings of the Selected Areas in Cryptography, 19th International Conference, 2012

2011

Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology.

Sumio Morioka, Toshiyuki Isshiki, Satoshi Obana, Yuichi Nakamura, Kazue Sako

Proceedings of the HOST 2011, 2011

2004

A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.

Sumio Morioka, Akashi Satoh

IEEE Trans. Very Large Scale Integr. Syst., 2004

2003

Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES.

Akashi Satoh, Sumio Morioka

Proceedings of the Information Security, 6th International Conference, 2003

Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia.

Akashi Satoh, Sumio Morioka

Proceedings of the Cryptographic Hardware and Embedded Systems, 2003

2002

Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI.

Akashi Satoh, Sumio Morioka

Proceedings of the Information Security, 5th International Conference, 2002

An Optimized S-Box Circuit Architecture for Low Power AES Design.

Sumio Morioka, Akashi Satoh

Proceedings of the Cryptographic Hardware and Embedded Systems, 2002

2001

Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2^m).

Sumio Morioka, Yasunao Katayama, Toshiyuki Yamane

Proceedings of the Computer Aided Verification, 13th International Conference, 2001

A Compact Rijndael Hardware Architecture with S-Box Optimization.

Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh

Proceedings of the Advances in Cryptology, 2001

2000

One-Shot Reed-Solomon Decoding for High-Performance Dependable Systems.

Yasunao Katayama, Sumio Morioka

Proceedings of the 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 2000

Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs.

Yasunao Katayama, Yasushi Negishi, Sumio Morioka

Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999

Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder.

Sumio Morioka, Yasunao Katayama

Proceedings of the IEEE International Conference On Computer Design, 1999

Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention.

Yasunao Katayama, Eric J. Stuckey, Sumio Morioka, Zhao Wu

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1994

Automatic Correctness Proof of the Implementation of Synchronous Sequential Circuits Using an Algebraic Approach.

Junji Kitamichi, Sumio Morioka, Teruo Higashino, Kenichi Taniguchi

Proceedings of the Theorem Provers in Circuit Design, 1994