Sumeet Kumar Gupta
Orcid: 0000-0001-5609-9722Affiliations:
- Purdue University, Elmore School of Electrical and Computer Engineering, West Lafayette, IN, USA
According to our database1,
Sumeet Kumar Gupta
authored at least 79 papers
between 2009 and 2025.
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Bibliography
2025
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2025
2024
Design Space Exploration for Phase Transition Material-Augmented MRAMs With Separate Read-Write Paths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024
BinSparX: Sparsified Binary Neural Networks for Reduced Hardware Non-Idealities in Xbar Arrays.
CoRR, 2024
SiTe CiM: Signed Ternary Computing-in-Memory for Ultra-Low Precision Deep Neural Networks.
CoRR, 2024
Comparative Evaluation of Memory Technologies for Synaptic Crossbar Arrays- Part 2: Design Knobs and DNN Accuracy Trends.
CoRR, 2024
SWANN: Shuffling Weights in Crossbar Arrays for Enhanced DNN Accuracy in Deeply Scaled Technologies.
CoRR, 2024
Memory Faults in Activation-sparse Quantized Deep Neural Networks: Analysis and Mitigation using Sharpness-aware Training.
CoRR, 2024
BNN-Flip: Enhancing the Fault Tolerance and Security of Compute-in-Memory Enabled Binary Neural Network Accelerators.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
Reimagining Sense Amplifiers: Harnessing Phase Transition Materials for Current and Voltage Sensing.
CoRR, 2023
Design Space Exploration and Comparative Evaluation of Memory Technologies for Synaptic Crossbar Arrays: Device-Circuit Non-Idealities and System Accuracy.
CoRR, 2023
XNOR-VSH: A Valley-Spin Hall Effect-based Compact and Energy-Efficient Synaptic Crossbar Array for Binary Neural Networks.
CoRR, 2023
CoRR, 2023
FeFET-Based Synaptic Cross-Bar Arrays for Deep Neural Networks: Impact of Ferroelectric Thickness on Device-Circuit Non-Idealities and System Accuracy.
Proceedings of the Device Research Conference, 2023
Analysis of Polarization Switching in HZO/ZrO2 (HZZ) Nanolaminates based on Sub-lattice Phase-field Model.
Proceedings of the Device Research Conference, 2023
TFix: Exploiting the Natural Redundancy of Ternary Neural Networks for Fault Tolerant In-Memory Vector Matrix Multiplication.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
Exploring the Design of Energy-Efficient Intermittently Powered Systems Using Reconfigurable Ferroelectric Transistors.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Valley-Spin Hall Effect-based Nonvolatile Memory with Exchange-Coupling-Enabled Electrical Isolation of Read and Write Paths.
CoRR, 2022
STeP-CiM: Strain-enabled Ternary Precision Computation-in-Memory based on Non-Volatile 2D Piezoelectric Transistors.
CoRR, 2022
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
2021
Monte Carlo Variation Analysis of NCFET-based 6-T SRAM: Design Opportunities and Trade-offs.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Exchange-Coupling-Enabled Electrical-Isolation of Compute and Programming Paths in Valley-Spin Hall Effect based Spintronic Device for Neuromorphic Applications.
Proceedings of the Device Research Conference, 2021
Proceedings of the Device Research Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
IPS-CiM: Enhancing Energy Efficiency of Intermittently-Powered Systems with Compute-in-Memory.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Polarization-induced Strain-coupled TMD FETs (PS FETs) for Non-Volatile Memory Applications.
Proceedings of the 2020 Device Research Conference, 2020
Utilizing Valley-Spin Hall Effect in WSe2 for Low Power Non-Volatile Flip-Flop Design.
Proceedings of the 2020 Device Research Conference, 2020
Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Des. Test, 2019
CoRR, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory Computation.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
2018
Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Dual Mode Ferroelectric Transistor based Non-Volatile Flip-Flops for Intermittently-Powered Systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Proceedings of the 2018 International Conference on IC Design & Technology, 2018
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
Proceedings of the 76th Device Research Conference, 2018
Proceedings of the 76th Device Research Conference, 2018
Modeling and Comparative Analysis of Hysteretic Ferroelectric and Anti-ferroelectric FETs.
Proceedings of the 76th Device Research Conference, 2018
Proceedings of the 76th Device Research Conference, 2018
Cockcroft-Walton Multiplier based on Unipolar Ag/HfO<sub>2</sub>/Pt Threshold Switch.
Proceedings of the 76th Device Research Conference, 2018
Proceedings of the 76th Device Research Conference, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells.
ACM J. Emerg. Technol. Comput. Syst., 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
On the potential of correlated materials in the design of spin-based cross-point memories (Invited).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
A High-Efficiency Switched-Capacitance HTFET Charge Pump for Low-Input-Voltage Applications.
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design Perspective.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
2014
Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
2013
ACM J. Emerg. Technol. Comput. Syst., 2013
IEEE Des. Test, 2013
2012
Low-Power Architecture for Epileptic Seizure Detection Based on Reduced Complexity DWT.
ACM J. Emerg. Technol. Comput. Syst., 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2010
Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device-Circuit-Architecture Codesign Perspective.
Proc. IEEE, 2010
2009
Proceedings of the 46th Design Automation Conference, 2009