Sumedh W. Sathaye

According to our database, Sumedh W. Sathaye authored at least 16 papers between 1995 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2006

Preface.

Erik R. Altman, Sumedh W. Sathaye

IBM J. Res. Dev., 2006

2001

Dynamic Binary Translation and Optimization.

Kemal Ebcioglu, Erik R. Altman, Michael Gschwind, Sumedh W. Sathaye

IEEE Trans. Computers, 2001

2000

System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design.

Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen

IEEE Trans. Very Large Scale Integr. Syst., 2000

Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility.

Thomas M. Conte, Sumedh W. Sathaye

IEEE Trans. Computers, 2000

Dynamic and Transparent Binary Translation.

Michael Gschwind, Erik R. Altman, Sumedh W. Sathaye, Paul Ledak, David Appenzeller

Computer, 2000

Binary translation and architecture convergence issues for IBM system/390.

Michael Gschwind, Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye

Proceedings of the 14th international conference on Supercomputing, 2000

1999

Optimizations and Oracle Parallelism with Dynamic Translation.

Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind

Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

Execution-Based Scheduling for VLIW Architectures.

Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind

Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998

MPS: Miss-Path Scheduling for Multiple-Issue Processors.

Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte

IEEE Trans. Computers, 1998

A Fast Interrupt Handling Scheme for VLIW Processors.

Emre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte

Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

1997

Optimization of VLIW compatibility systems employing dynamic rescheduling.

Thomas M. Conte, Sumedh W. Sathaye

Int. J. Parallel Program., 1997

Path Prediction for High Issue-Rate Processors.

Kishore N. Menezes, Sumedh W. Sathaye, Thomas M. Conte

Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997

1996

A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures.

Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings.

Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

1995

Dynamic rescheduling: a technique for object code compatibility in VLIW architectures.

Thomas M. Conte, Sumedh W. Sathaye

Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

A technique to determine power-efficient, high-performance superscalar processors.

Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye

Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995