Sumanta Chaudhuri

Jean-Luc Danger

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

WaterMAS: Sharpness-Aware Maximization for Neural Network Watermarking.

[BibT_eX]

[DOI]

Proceedings of the Pattern Recognition - 27th International Conference, 2024

Find the Lady: Permutation and Re-synchronization of Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023

A gem5 based Platform for Micro-Architectural Security Analysis.

[BibT_eX]

[DOI]

Quentin Forcioli

Jean-Luc Danger

Proceedings of the 12th International Workshop on Hardware and Architectural Support for Security and Privacy, 2023

A Hitchhiker's Guide to White-Box Neural Network Watermarking Robustness.

[BibT_eX]

[DOI]

Proceedings of the 11th European Workshop on Visual Information Processing, 2023

2022

Minconvnets: a New Class of Multiplication-Less Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Image Processing, 2022

2020

Quad-Approx CNNs for Embedded Object Detection Systems.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2018

Beyond Bits: A Quaternary FPGA Architecture Using Multi-Vt Multi-Vdd FDSOI Devices.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

A security vulnerability analysis of SoCFPGA architectures.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Cache Timing Attacks from The SoCFPGA Coherency Port (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016

Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology.

[BibT_eX]

[DOI]

Tarik Graba

Yves Mathieu

CoRR, 2016

2014

Mitigation of process variation effect in FPGAs with partial rerouting method.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

Classification on variation maps: a new placement strategy to alleviate process variation on FPGA.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

2013

Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

A variation-adaptive retiming method exploiting reconfigurability.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012

Cross-point architecture for spin transfer torque magnetic random access memory

[BibT_eX]

[DOI]

Weisheng Zhao

Celso Accoto

Jacques-Olivier Klein

Claude Chappert

Pascale Mazoyer

CoRR, 2012

A two-stage variation-aware placement method for FPGAS exploiting variation maps classification.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011

Side-Channel Oscilloscope

[BibT_eX]

[DOI]

Sylvain Guilley

CoRR, 2011

A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback

[BibT_eX]

[DOI]

CoRR, 2011

Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

2010

Design of embedded MRAM macros for memory-in-logic applications.

[BibT_eX]

[DOI]

Weisheng Zhao

Jacques-Olivier Klein

Claude Chappert

Pascale Mazoyer

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

High Density Asynchronous LUT Based on Non-volatile MRAM Technology.

[BibT_eX]

[DOI]

Weisheng Zhao

Jacques-Olivier Klein

Claude Chappert

Pascale Mazoyer

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009

Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Diagonal tracks in FPGAs: a performance evaluation.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008

Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks

[BibT_eX]

[DOI]

CoRR, 2008

Place-and-Route Impact on the Security of DPL Designs in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

Efficient tiling patterns for reconfigurable gate arrays.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

An 8x8 run-time reconfigurable FPGA embedded in a SoC.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Physical Design of FPGA Interconnect to Prevent Information Leakage.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2008

2007

A Reconfigurable Cell for a Multi-Style Asynchronous FPGA.

[BibT_eX]

Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

A Novel Asynchronous e-FPGA Architecture for Security Applications.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Efficient Modeling and Floorplanning of Embedded-FPGA Fabric.

[BibT_eX]

[DOI]