Sukru Burc Eryilmaz

According to our database, Sukru Burc Eryilmaz authored at least 13 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

ScaleFold: Reducing AlphaFold Initial Training Time to 10 Hours.

Feiwen Zhu, Arkadiusz Nowaczynski, Rundong Li, Jie Xin, Yifei Song, Michal Marcinkiewicz, Sukru Burc Eryilmaz, Jun Yang, Michael Andersch

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Understanding How Orthogonality of Parameters Improves Quantization of Neural Networks.

Sukru Burc Eryilmaz, Aysegul Dundar

IEEE Trans. Neural Networks Learn. Syst., December, 2023

FastDimeNet++: Training DimeNet++ in 22 minutes.

Feiwen Zhu, Michal Futrega, Han Bao, Sukru Burc Eryilmaz, Fei Kong, Kefeng Duan, Xinnian Zheng, Nimrod Angel, Matthias Jouanneaux, Maxmilian Stadler, Michal Marcinkiewicz, Fung Xie, June Yang, Michael Andersch

Proceedings of the 52nd International Conference on Parallel Processing, 2023

2022

A compute-in-memory chip based on resistive random-access memory.

Weier Wan, Rajkumar Kubendran, Clemens J. S. Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen R. Deiss, Priyanka Raina, He Qian, Bin Gao, Siddharth Joshi, Huaqiang Wu, H.-S. Philip Wong, Gert Cauwenberghs

Nat., 2022

2021

Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory.

Weier Wan, Rajkumar Kubendran, Clemens J. S. Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen R. Deiss, Priyanka Raina, He Qian, Bin Gao, Siddharth Joshi, Huaqiang Wu, H.-S. Philip Wong, Gert Cauwenberghs

CoRR, 2021

2020

33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models.

Weier Wan, Rajkumar Kubendran, Sukru Burc Eryilmaz, Wenqiang Zhang, Yan Liao, Dabin Wu, Stephen R. Deiss, Bin Gao, Priyanka Raina, Siddharth Joshi, Huaqiang Wu, Gert Cauwenberghs, H.-S. Philip Wong

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2017

Opportunities for Analog Coding in Emerging Memory Systems.

Jesse H. Engel, Sukru Burc Eryilmaz, SangBum Kim, Matthew BrightSky, Chung Lam, Hsiang-Lan Lung, Bruno A. Olshausen, H.-S. Philip Wong

CoRR, 2017

2016

Training a Probabilistic Graphical Model with Resistive Switching Electronic Synapses.

Sukru Burc Eryilmaz, Emre Neftci, Siddharth Joshi, SangBum Kim, Matthew BrightSky, Hsiang-Lan Lung, Chung Lam, Gert Cauwenberghs, H.-S. Philip Wong

CoRR, 2016

Neuromorphic architectures with electronic synapses.

Sukru Burc Eryilmaz, Siddharth Joshi, Emre Neftci, Weier Wan, Gert Cauwenberghs, H.-S. Philip Wong

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015

Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures.

Sukru Burc Eryilmaz, Duygu Kuzum, Shimeng Yu, H.-S. Philip Wong

CoRR, 2015

2014

Experimental Demonstration of Array-level Learning with Phase Change Synaptic Devices.

Sukru Burc Eryilmaz, Duygu Kuzum, Rakesh Gnana David Jeyasingh, SangBum Kim, Matthew BrightSky, Chung Lam, H.-S. Philip Wong

CoRR, 2014

Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array.

Sukru Burc Eryilmaz, Duygu Kuzum, Rakesh Gnana David Jeyasingh, SangBum Kim, Matthew BrightSky, Chung Lam, H.-S. Philip Wong

CoRR, 2014

Supervised classification-based stock prediction and portfolio optimization.

Sercan Ö. Arik, Sukru Burc Eryilmaz, Adam Goldberg

CoRR, 2014