Sukeshwar Kannan

According to our database, Sukeshwar Kannan authored at least 22 papers between 2009 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs.

Arjun Chaudhuri, Sanmitra Banerjee, Jinwoo Kim, Heechun Park, Bon Woong Ku, Sukeshwar Kannan, Krishnendu Chakrabarty, Sung Kyu Lim

ACM J. Emerg. Technol. Comput. Syst., 2022

2020

Accelerating Artificial Intelligence with Silicon Photonics.

Nicholas C. Harris, Ryan Braid, Darius Bunandar, Jim Carr, Brad Dobbie, Carlos Dorta-Quinones, Jon Elmhurst, Martin Forsythe, Michael Gould, Shashank Gupta, Sukeshwar Kannan, Tyler Kenney, Gary Kong, Tomo Lazovich, Scott Mckenzie, Carl Ramey, Chithira Ravi, Michael Scott, John Sweeney, Ozgur Yildirim, Katrina Zhang

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020

2019

A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits.

Abhishek Koneru, Sukeshwar Kannan, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Compact Scalable Dynamic TSV IR Drop Compensation for Power Delivery in 3D Packages.

Arjun Chaudhuri, Sukeshwar Kannan, Luke England, Jack Golz

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2017

Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs.

Ran Wang, Zipeng Li, Sukeshwar Kannan, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors.

Mehdi Sadi, Sukeshwar Kannan, LeRoy Winemberg, Mark M. Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits.

Abhishek Koneru, Sukeshwar Kannan, Krishnendu Chakrabarty

ACM J. Emerg. Technol. Comput. Syst., 2017

Design of a digital IP for 3D-IC die-to-die clock synchronization.

Mehdi Sadi, Sukeshwar Kannan, Luke England, Mark M. Tehranipoor

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A Design-for-Test Solution for Monolithic 3D Integrated Circuits.

Abhishek Koneru, Sukeshwar Kannan, Krishnendu Chakrabarty

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016

Power delivery in 3D packages: current crowding effects, dynamic IR drop and compensation network using sensors (invited paper).

Sukeshwar Kannan, Mehdi Sadi, Luke England

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Pre-bond testing of the silicon interposer in 2.5D ICs.

Ran Wang, Zipeng Li, Sukeshwar Kannan, Krishnendu Chakrabarty

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Impact of TSV integration on 14nm FinFET device performance.

Luke England, Sukeshwar Kannan, Rahul Agarwal, Daniel Smith

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015

Device performance analysis on 20nm technology thin wafers in a 3D package.

Sukeshwar Kannan, Rahul Agarwal, Arnaud Bousquet, Geetha Aluri, Hui-Shan Chang

Proceedings of the IEEE International Reliability Physics Symposium, 2015

2013

Physics-Based Low-Cost Test Technique for High Voltage LDMOS.

Sukeshwar Kannan, Kaushal Kannan, Bruce C. Kim, Friedrich Taenzler, Richard Antley, Ken Moushegian, Kenneth M. Butler, Doug Mirizzi

J. Electron. Test., 2013

Physics Based Fault Models for Testing High-Voltage LDMOS.

Sukeshwar Kannan, Bruce C. Kim, Anurag Gupta, Friedrich Taenzler, Richard Antley, Ken Moushegian

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Development of hybrid electrical model for CNT based Through Silicon Vias.

Kaushal Kannan, Sukeshwar Kannan, Bruce C. Kim, Sang-Bock Cho

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects.

Sukeshwar Kannan, Bruce C. Kim, Byoungchul Ahn

J. Electron. Test., 2012

Modeling and characterization of CNT-based TSV for high frequency applications.

Sukeshwar Kannan, Bruce C. Kim, Anurag Gupta, Seok-Ho Noh, Li Li, Sang-Bock Cho

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Analysis of propagation delay in 3 - D stacked DRAM.

Sukeshwar Kannan, Bruce C. Kim, Sang-Bock Cho, Byoungchul Ahn

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

Embedded RF Circuit Diagnostic Technique with Multi-Tone Dither Scheme.

Sukeshwar Kannan, Bruce C. Kim, Ganesh Srinivasan, Friedrich Taenzler, Richard Antley, Craig Force

J. Electron. Test., 2011

2010

RADPro: Automatic RF analyzer and diagnostic program generation tool.

Sukeshwar Kannan, Bruce C. Kim, Ganesh Srinivasan, Friedrich Taenzlar, Richard Antley, Craig Force, Falah Mohammed

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

Automatic diagnostic tool for Analog-Mixed Signal and RF load boards.

Sukeshwar Kannan, Bruce C. Kim

Proceedings of the 2009 IEEE International Test Conference, 2009