Sukarn Agarwal

According to our database, Sukarn Agarwal authored at least 24 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment.

Sangeet Saha, Shounak Chakraborty, Sukarn Agarwal, Magnus Själander, Klaus D. McDonald-Maier

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture.

Sukarn Agarwal, Shounak Chakraborty, Magnus Själander

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

2023

DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore.

Sangeet Saha, Shounak Chakraborty, Sukarn Agarwal, Rahul Gangopadhyay, Magnus Själander, Klaus D. McDonald-Maier

IEEE Trans. Parallel Distributed Syst., February, 2023

Compound Memory Models.

Andrés Goens, Soham Chakraborty, Susmit Sarkar, Sukarn Agarwal, Nicolai Oswald, Vijay Nagarajan

Proc. ACM Program. Lang., 2023

Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR).

Sukarn Agarwal, Shounak Chakraborty, Magnus Själander

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2021

Improving the Performance of Hybrid Caches Using Partitioned Victim Caching.

Sukarn Agarwal, Hemangee K. Kapoor

ACM Trans. Embed. Comput. Syst., 2021

DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches.

Mayank Baranwal, Udbhav Chugh, Shivang Dalal, Sukarn Agarwal, Hemangee K. Kapoor

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache.

Sukarn Agarwal, Shounak Chakraborty

Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020

Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System.

Arijit Nath, Sukarn Agarwal, Hemangee K. Kapoor

ACM Trans. Design Autom. Electr. Syst., 2020

LiNoVo: Longevity Enhancement of Non-Volatile Last Level Caches in Chip Multiprocessors.

Sukarn Agarwal, Hemangee K. Kapoor

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects.

Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

2019

Improving the Lifetime of Non-Volatile Cache by Write Restriction.

Sukarn Agarwal, Hemangee K. Kapoor

IEEE Trans. Computers, 2019

Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks.

Sheel Sindhu Manohar, Sukarn Agarwal, Hemangee K. Kapoor

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Enhancing the Lifetime of Non-Volatile Caches by Exploiting Module-Wise Write Restriction.

Sukarn Agarwal, Hemangee K. Kapoor

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018

Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches.

Sukarn Agarwal, Hemangee K. Kapoor

IEEE Trans. Very Large Scale Integr. Syst., 2018

Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets.

Sharma Priya, Sukarn Agarwal, Hemangee K. Kapoor

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors.

Ashwini A. Kulkarni, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon.

Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor

Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors.

Ashwini A. Kulkarni, Chirag Joshi, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor

Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

2017

Towards a Better Lifetime for Non-volatile Caches in Chip Multiprocessors.

Sukarn Agarwal, Hemangee K. Kapoor

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques.

Sukarn Agarwal, Hemangee K. Kapoor

Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017

Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets.

Sukarn Agarwal, Hemangee K. Kapoor

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

2016

Restricting writes for energy-efficient hybrid cache in multi-core architectures.

Sukarn Agarwal, Hemangee K. Kapoor

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Towards a dynamic associativity enabled write prediction based hybrid cache.

Sukarn Agarwal, Hemangee K. Kapoor

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016