Sujoy Sinha Roy
Orcid: 0000-0002-9805-5389
According to our database1,
Sujoy Sinha Roy
authored at least 86 papers
between 2011 and 2024.
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Bibliography
2024
IEEE Trans. Very Large Scale Integr. Syst., July, 2024
High-Speed Design of Post Quantum Cryptography With Optimized Hashing and Multiplication.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024
ModHE: Modular Homomorphic Encryption Using Module Lattices Potentials and Limitations.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024
OpenNTT: An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHE.
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security, 2024
REPQC: Reverse Engineering and Backdooring Hardware Accelerators for Post-quantum Cryptography.
Proceedings of the 19th ACM Asia Conference on Computer and Communications Security, 2024
2023
J. Cryptogr. Eng., November, 2023
IEEE Trans. Computers, June, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023
Kavach: Lightweight masking techniques for polynomial arithmetic in lattice-based cryptography.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023
Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption.
IACR Cryptol. ePrint Arch., 2023
IACR Cryptol. ePrint Arch., 2023
IACR Cryptol. ePrint Arch., 2023
IACR Cryptol. ePrint Arch., 2023
PROTEUS: A Tool to generate pipelined Number Theoretic Transform Architectures for FHE and ZKP applications.
IACR Cryptol. ePrint Arch., 2023
IACR Cryptol. ePrint Arch., 2023
Secure and Efficient Post-Quantum Cryptography in Hardware and Software (Dagstuhl Seminar 23152).
Dagstuhl Reports, 2023
2022
On Exploiting Message Leakage in (Few) NIST PQC Candidates for Practical Message Recovery Attacks.
IEEE Trans. Inf. Forensics Secur., 2022
Will You Cross the Threshold for Me? Generic Side-Channel Assisted Chosen-Ciphertext Attacks on NTRU-based KEMs.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
IEEE Trans. Computers, 2022
Magnifying Side-Channel Leakage of Lattice-Based Cryptosystems With Chosen Ciphertexts: The Case Study of Kyber.
IEEE Trans. Computers, 2022
IACR Cryptol. ePrint Arch., 2022
2021
IACR Cryptol. ePrint Arch., 2021
IACR Cryptol. ePrint Arch., 2021
2020
High-speed Instruction-set Coprocessor for Lattice-based Key Encapsulation Mechanism: Saber in Hardware.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020
IEEE Trans. Computers, 2020
Magnifying Side-Channel Leakage of Lattice-Based Cryptosystems with Chosen Ciphertexts: The Case Study of Kyber.
IACR Cryptol. ePrint Arch., 2020
On Exploiting Message Leakage in (few) NIST PQC Candidates for Practical Message Recovery and Key Recovery Attacks.
IACR Cryptol. ePrint Arch., 2020
Drop by Drop you break the rock - Exploiting generic vulnerabilities in Lattice-based PKE/KEMs using EM-based Physical Attacks.
IACR Cryptol. ePrint Arch., 2020
Compact domain-specific co-processor for accelerating module lattice-based key encapsulation mechanism.
IACR Cryptol. ePrint Arch., 2020
IACR Cryptol. ePrint Arch., 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
FPGA-based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data.
IACR Cryptol. ePrint Arch., 2019
SaberX4: High-throughput Software Implementationof Saber Key Encapsulation Mechanism.
IACR Cryptol. ePrint Arch., 2019
IACR Cryptol. ePrint Arch., 2019
Pushing the speed limit of constant-time discrete Gaussian sampling. A case study on Falcon.
IACR Cryptol. ePrint Arch., 2019
SaberX4: High-Throughput Software Implementation of Saber Key Encapsulation Mechanism.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Pushing the speed limit of constant-time discrete Gaussian sampling. A case study on the Falcon signature scheme.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018
HEPCloud: An FPGA-Based Multicore Processor for FV Somewhat Homomorphic Function Evaluation.
IEEE Trans. Computers, 2018
Arithmetic of $$\tau $$ τ -adic expansions for lightweight Koblitz curve cryptography.
J. Cryptogr. Eng., 2018
IACR Cryptol. ePrint Arch., 2018
Proceedings of the 12th European Workshop on Microelectronics Education, 2018
2017
Public Key Cryptography on Hardware Platforms: Design and Analysis of Elliptic Curve and Lattice-based Cryptoprocessors ; Public key cryptografie op hardware platforms: ontwerp en analyse van elliptische krommen en rooster-gebaseerde crypto-processors.
PhD thesis, 2017
ACM Trans. Embed. Comput. Syst., 2017
IEEE Trans. Computers, 2017
2016
IACR Cryptol. ePrint Arch., 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
A Tiny Coprocessor for Elliptic Curve Cryptography over the 256-bit NIST Prime Field.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016
Proceedings of the Post-Quantum Cryptography - 7th International Workshop, 2016
2015
Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms.
IEEE Trans. Very Large Scale Integr. Syst., 2015
High-Speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IACR Cryptol. ePrint Arch., 2015
Lightweight Coprocessor for Koblitz Curves: 283-bit ECC Including Scalar Conversion with only 4300 Gates.
IACR Cryptol. ePrint Arch., 2015
IACR Cryptol. ePrint Arch., 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
IACR Cryptol. ePrint Arch., 2014
IACR Cryptol. ePrint Arch., 2014
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2014, 2014
2013
Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IACR Cryptol. ePrint Arch., 2013
Proceedings of the Selected Areas in Cryptography - SAC 2013, 2013
2012
Integr., 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Pushing the Limits of High-Speed GF(2 m ) Elliptic Curve Scalar Multiplication on FPGAs.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IACR Cryptol. ePrint Arch., 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Theoretical modeling of the Itoh-Tsujii Inversion algorithm for enhanced performance on k-LUT based FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2011