Sujith Billa

According to our database, Sujith Billa authored at least 6 papers between 2016 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density.

Raviteja Theertham, Prasanth Koottala, Sujith Billa, Shanthi Pavan

IEEE J. Solid State Circuits, 2020

Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator.

Sujith Billa, Suhas Dixit, Shanthi Pavan

IEEE J. Solid State Circuits, 2020

2019

A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth.

Raviteja Theertham, Prasanth Koottala, Sujith Billa, Shanthi Pavan

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 265μW Continuous-Time 1-2 MASH ADC Achieving 100.6 dB SNDR in a 24 kHz Bandwidth.

Sujith Billa, Suhas Dixit, Shanthi Pavan

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2017

Analysis and Design of Continuous-Time Delta-Sigma Converters Incorporating Chopping.

Sujith Billa, Amrith Sukumaran, Shanthi Pavan

IEEE J. Solid State Circuits, 2017

2016

15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts.

Sujith Billa, Amrith Sukumaran, Shanthi Pavan

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016