Sujit Dey

Orcid: 0000-0001-9671-3950

Affiliations:
  • University of California, San Diego, USA


According to our database1, Sujit Dey authored at least 248 papers between 1988 and 2024.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2014, "For contributions to the design and testing of low-power systems and system-on-chips".

Timeline

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Bibliography

2024
SLEXNet: Adaptive Inference Using Slimmable Early Exit Neural Networks.
ACM Trans. Embed. Comput. Syst., November, 2024

Multi-Modal Data and Model Reduction for Enabling Edge Fusion in Connected Vehicle Environments.
IEEE Trans. Veh. Technol., August, 2024

Optimal Vehicle Charging in Bilevel Power-Traffic Networks via Charging Demand Function.
IEEE Trans. Smart Grid, May, 2024

Utilizing Reinforcement Learning for Adaptive Sensor Data Sharing Over C-V2X Communications.
IEEE Trans. Veh. Technol., March, 2024

Body and Head Orientation Estimation From Low-Resolution Point Clouds in Surveillance Settings.
IEEE Access, 2024

Fast and Scalable Design Space Exploration for Deep Learning on Embedded Systems.
IEEE Access, 2024

BRIC: Bottom-Up Residual Vector Quantization for Learned Image Compression.
IEEE Access, 2024

Attention-Based Multi-Modal Multi-View Fusion Approach for Driver Facial Expression Recognition.
IEEE Access, 2024

Graph-Based Multi-Modal Multi-View Fusion for Facial Action Unit Recognition.
IEEE Access, 2024

Personalized Impact of Lifestyle on Type 1 Diabetes Patients: A Comprehensive Regression Analysis.
Proceedings of the 12th IEEE International Conference on Healthcare Informatics, 2024

2023
Uncertainty-Aware Task Offloading for Multi-Vehicle Perception Fusion Over Vehicular Edge Computing.
IEEE Trans. Veh. Technol., November, 2023

GaMiCO: Game-slicing based multi-interface computation offloading in 5G vehicular networks.
J. Commun. Networks, August, 2023

Classification of Patient Recovery From COVID-19 Symptoms Using Consumer Wearables and Machine Learning.
IEEE J. Biomed. Health Informatics, March, 2023

Analyzing Head Orientation of Neurotypical and Autistic Individuals in Triadic Conversations.
CoRR, 2023

EvoSh: Evolutionary Search with Shaving to Enable Power-Latency Tradeoff in Deep Learning Computing on Embedded Systems.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Short: Deep Learning Approach to Skeletal Performance Evaluation of Physical Therapy Exercises.
Proceedings of the IEEE/ACM Conference on Connected Health: Applications, 2023

2022
Contention Grading and Adaptive Model Selection for Machine Vision in Embedded Systems.
ACM Trans. Embed. Comput. Syst., September, 2022

Personalized Blood Pressure Estimation Using Photoplethysmography: A Transfer Learning Approach.
IEEE J. Biomed. Health Informatics, 2022

Multi-Source Feature Fusion for Object Detection Association in Connected Vehicle Environments.
IEEE Access, 2022

Adaptive C-V2X Sidelink Communications for Vehicular Applications Beyond Safety Messages.
Proceedings of the 95th IEEE Vehicular Technology Conference, 2022

An mHealth Lifestyle Intervention Service for Improving Blood Pressure using Machine Learning and IoMTs.
Proceedings of the IEEE International Conference on Digital Health, 2022

2021
Adaptive Computation Partitioning and Offloading in Real-Time Sustainable Vehicular Edge Computing.
IEEE Trans. Veh. Technol., 2021

Predictive Adaptive Streaming to Enable Mobile 360-Degree and VR Experiences.
IEEE Trans. Multim., 2021

Low Overhead Codebook Design for mmWave Roadside Units Placed at Smart Intersections.
Proceedings of the 32nd IEEE Annual International Symposium on Personal, 2021

Multi-Modal Fusion Enhanced Model For Driver's Facial Expression Recognition.
Proceedings of the 2021 IEEE International Conference on Multimedia & Expo Workshops, 2021

Body and Head Orientation Estimation with Privacy Preserving LiDAR Sensors.
Proceedings of the 29th European Signal Processing Conference, 2021

Contention-aware Adaptive Model Selection for Machine Vision in Embedded Systems.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
Real-Time QoS Optimization for Vehicular Edge Computing With Off-Grid Roadside Units.
IEEE Trans. Veh. Technol., 2020

Motion Prediction and Pre-Rendering at the Edge to Enable Ultra-Low Latency Mobile 6DoF Experiences.
IEEE Open J. Commun. Soc., 2020

Using Sensors and Deep Learning to Enable On-Demand Balance Evaluation for Effective Physical Therapy.
IEEE Access, 2020

X-Array: approximating omnidirectional millimeter-wave coverage using an array of phased arrays.
Proceedings of the MobiCom '20: The 26th Annual International Conference on Mobile Computing and Networking, 2020

Vehicular and Edge Computing for Emerging Connected and Autonomous Vehicle Applications.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Machine Learning Techniques for Vehicle Matching with Non-Overlapping Visual Features.
Proceedings of the 3rd IEEE Connected and Automated Vehicles Symposium, 2020

2019
User performance evaluation and real-time guidance in cloud-based physical therapy monitoring and guidance system.
Multim. Tools Appl., 2019

Offline and Online Learning Techniques for Personalized Blood Pressure Prediction and Health Behavior Recommendations.
IEEE Access, 2019

Sustainable Vehicular Edge Computing Using Local and Solar-Powered Roadside Unit Resources.
Proceedings of the 90th IEEE Vehicular Technology Conference, 2019

Center of Mass Estimation for Balance Evaluation Using Convolutional Neural Networks.
Proceedings of the 2019 IEEE International Conference on Healthcare Informatics, 2019

Personalized Blood Pressure Estimation using Photoplethysmography and Wavelet Decomposition.
Proceedings of the 2019 IEEE International Conference on E-health Networking, 2019

Head and Body Motion Prediction to Enable Mobile VR Experiences with Low Latency.
Proceedings of the 2019 IEEE Global Communications Conference, 2019

2018
Novel Hybrid-Cast Approach to Reduce Bandwidth and Latency for Cloud-Based Virtual Space.
ACM Trans. Multim. Comput. Commun. Appl., 2018

Optimal Use of Harvested Solar, Hybrid Storage and Base Station Resources for Green Cellular Networks.
IEEE Trans. Green Commun. Netw., 2018

Predictive View Generation to Enable Mobile 360-degree and VR Experiences.
Proceedings of the 2018 Morning Workshop on Virtual Reality and Augmented Reality Network, 2018

Human Action Understanding and Movement Error Identification for the Treatment of Patients with Parkinson's Disease.
Proceedings of the IEEE International Conference on Healthcare Informatics, 2018

Quality of Service Optimization for Vehicular Edge Computing with Solar-Powered Road Side Units.
Proceedings of the 27th International Conference on Computer Communication and Networks, 2018

Personalized Effect of Health Behavior on Blood Pressure: Machine Learning Based Prediction and Recommendation.
Proceedings of the 20th IEEE International Conference on e-Health Networking, 2018

2017
User QoS-Aware Adaptive RF Chain Switching for Power Efficient Cooperative Base Stations.
IEEE Trans. Green Commun. Netw., 2017

Asymmetric and selective object rendering for optimized Cloud Mobile 3D Display Gaming user experience.
Multim. Tools Appl., 2017

Energy Efficient Hybrid Beamforming in Massive MU-MIMO Systems via Eigenmode Selection.
Proceedings of the 2017 IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, 2017

Wireless VR/AR with Edge/Cloud Computing.
Proceedings of the 26th International Conference on Computer Communication and Networks, 2017

2016
Emulation-Based Analysis of System-on-Chip Performance Under Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Enhancing Mobile Video Capacity and Quality Using Rate Adaptation, RAN Caching and Processing.
IEEE/ACM Trans. Netw., 2016

Dynamic cell reconfiguration framework for energy conservation in cellular wireless networks.
J. Commun. Networks, 2016

JAVRE: A Joint Asymmetric Video Rendering and Encoding Approach to Enable Optimized Cloud Mobile 3D Virtual Immersive User Experience.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Improving Scalability of Personalized Recommendation Systems for Enterprise Knowledge Workers.
IEEE Access, 2016

A Novel Hyper-Cast Approach to Enable Cloud-Based Virtual Classroom Applications.
Proceedings of the IEEE International Symposium on Multimedia, 2016

2015
Joint Work and Voltage/Frequency Scaling for Quality-Optimized Dynamic Thermal Management.
IEEE Trans. Very Large Scale Integr. Syst., 2015

An Application Adaptation Approach to Mitigate the Impact of Dynamic Thermal Management on Video Encoding.
ACM Trans. Design Autom. Electr. Syst., 2015

Battery Aware Video Delivery Techniques Using Rate Adaptation and Base Station Reconfiguration.
IEEE Trans. Multim., 2015

Enhancing Video Encoding for Cloud Gaming Using Rendering Information.
IEEE Trans. Circuits Syst. Video Technol., 2015

Deriving and Validating User Experience Model for DASH Video Streaming.
IEEE Trans. Broadcast., 2015

Cloud Mobile 3D Display Gaming User Experience Modeling and Optimization by Asymmetric Graphics Rendering.
IEEE J. Sel. Top. Signal Process., 2015

Construction and evaluation of ontological tag trees.
Expert Syst. Appl., 2015

Methods to Obtain Training Videos for Fully Automated Application-Specific Classification.
IEEE Access, 2015

Motion data alignment and real-time guidance in cloud-based virtual training system.
Proceedings of the conference on Wireless Health, 2015

Renewable energy-aware video download in cellular networks.
Proceedings of the 26th IEEE Annual International Symposium on Personal, 2015

A Joint Asymmetric Graphics Rendering and Video Encoding Approach for Optimizing Cloud Mobile 3D Display Gaming User Experience.
Proceedings of the 2015 IEEE International Symposium on Multimedia, 2015

Access Prediction for Knowledge Workers in Enterprise Data Repositories.
Proceedings of the ICEIS 2015, 2015

Optimizing Cloud Mobile 3D Display Gaming user experience by asymmetric object of interest rendering.
Proceedings of the 2015 IEEE International Conference on Communications, 2015

Power-efficient base station operation through user QoS-aware adaptive RF chain switching technique.
Proceedings of the 2015 IEEE International Conference on Communications, 2015

Motion data alignment for real-time guidance in avatar based physical therapy training system.
Proceedings of the 17th International Conference on E-health Networking, 2015

2014
Video-Aware Scheduling and Caching in the Radio Access Network.
IEEE/ACM Trans. Netw., 2014

Content-Aware Modeling and Enhancing User Experience in Cloud Mobile Rendering and Streaming.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Construction of tag ontological graphs by locally minimizing weighted average hops.
Proceedings of the 23rd International World Wide Web Conference, 2014

Mobile device video caching to improve video qoe and cellular network capacity.
Proceedings of the 17th ACM International Conference on Modeling, 2014

Variation tolerant design of a vector processor for recognition, mining and synthesis.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Enhancing Cloud Mobile 3D display gaming user experience by asymmetric graphics rendering.
Proceedings of the International Conference on Computing, Networking and Communications, 2014

Variation Aware Cache Partitioning for Multithreaded Programs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Adaptive Mobile Cloud Computing to Enable Rich Mobile Multimedia Applications.
IEEE Trans. Multim., 2013

Fully Automated Learning for Application-Specific Web Video Classification.
Proceedings of the 2013 IEEE/WIC/ACM International Conferences on Web Intelligence, 2013

QoS-aware dynamic cell reconfiguration for energy conservation in cellular networks.
Proceedings of the 2013 IEEE Wireless Communications and Networking Conference (WCNC), 2013

Rate adaptation and base station reconfiguration for battery efficient video download.
Proceedings of the 2013 IEEE Wireless Communications and Networking Conference (WCNC), 2013

Adaptive Bit Rate capable video caching and scheduling.
Proceedings of the 2013 IEEE Wireless Communications and Networking Conference (WCNC), 2013

User Experience Modeling for DASH Video.
Proceedings of the 20th International Packet Video Workshop, 2013

2012
Variation-Aware Voltage Level Selection.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Cloud mobile gaming: modeling and measuring user experience in mobile wireless networks.
ACM SIGMOBILE Mob. Comput. Commun. Rev., 2012

Video caching in Radio Access Network: Impact on delay and capacity.
Proceedings of the 2012 IEEE Wireless Communications and Networking Conference, 2012

Modeling, characterizing, and enhancing user experience in Cloud Mobile Rendering.
Proceedings of the International Conference on Computing, Networking and Communications, 2012

Cloud Mobile Media: Opportunities, challenges, and directions.
Proceedings of the International Conference on Computing, Networking and Communications, 2012

Wireless network aware cloud scheduler for scalable cloud mobile gaming.
Proceedings of IEEE International Conference on Communications, 2012

Hierarchical video caching in wireless cloud: Approaches and algorithms.
Proceedings of IEEE International Conference on Communications, 2012

Adaptation of video encoding to address dynamic thermal management effects.
Proceedings of the 2012 International Green Computing Conference, 2012

Recovery-based design for variation-tolerant SoCs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
VESPA: Variability emulation for System-on-Chip performance analysis.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Variation-Aware System-Level Power Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Addressing Response Time and Video Quality in Remote Server Based Internet Mobile Gaming.
Proceedings of the 2010 IEEE Wireless Communications and Networking Conference, 2010

Rendering Adaptation to Address Communication and Computation Constraints in Cloud Mobile Gaming.
Proceedings of the Global Communications Conference, 2010

2009
Variation-Tolerant Dynamic Power Management at the System-Level.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Model-Based Techniques for Data Reliability in Wireless Sensor Networks.
IEEE Trans. Mob. Comput., 2009

Enabling rich mobile applications: joint computation and communication scheduling.
ACM SIGMOBILE Mob. Comput. Commun. Rev., 2009

Coping with Variations through System-Level Design.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Modeling and Characterizing User Experience in a Cloud Server Based Mobile Gaming Approach.
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

2008
Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication.
IEEE Trans. Very Large Scale Integr. Syst., 2008

2007
Dynamic adaptation policies to improve quality of service of real-time multimedia applications in IEEE 802.11e WLAN Networks.
Wirel. Networks, 2007

Evaluating Transient Error Effects in Digital Nanometer Circuits.
IEEE Trans. Reliab., 2007

A Device and Network-Aware Scaling Framework for Efficient Delivery of Scalable Video over Wireless Networks.
Proceedings of the IEEE 18th International Symposium on Personal, 2007

Modeling soft error effects considering process variations.
Proceedings of the 25th International Conference on Computer Design, 2007

Joint Computation and Communication Scheduling to Enable Rich Mobile Applications.
Proceedings of the Global Communications Conference, 2007

System-on-Chip Power Management Considering Leakage Power Variations.
Proceedings of the 44th Design Automation Conference, 2007

2006
Evaluating and Improving Transient Error Tolerance of CMOS Digital VLSI Circuits.
Proceedings of the 2006 IEEE International Test Conference, 2006

Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO).
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Considering process variations during system-level power analysis.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Quality of service provisioning in 802.11e networks: challenges, approaches, and future directions.
IEEE Netw., 2005

Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits.
IEEE Des. Test Comput., 2005

Dynamic end-to-end image adaptation for guaranteed quality of service in wireless image data services.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2005

A static noise impact analysis methodology for evaluating transient error effects in digital VLSI circuits.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Addressing Computational and Networking Constraints to Enable Video Streaming from Wireless Appliances.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits.
Proceedings of the 42nd Design Automation Conference, 2005

FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Optimizing designs using the addition of deflection operations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Resource budgeting for Multiprocess High-level synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Common-case computation: a high-level energy and performance optimization technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Design of high-performance system-on-chips using communication architecture tuners.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Design space exploration for optimizing on-chip communication architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Efficient power profiling for battery-driven embedded system design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

High-level crosstalk defect Simulation methodology for system-on-chip interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Data aware, low cost error correction for wireless sensor networks.
Proceedings of the 2004 IEEE Wireless Communications and Networking Conference , 2004

Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Model based error correction for wireless sensor networks.
Proceedings of the First Annual IEEE Communications Society Conference on Sensor and Ad Hoc Communications and Networks, 2004

CHASER: content and channel aware object scheduling and error control for wireless Web access in 3G networks.
Proceedings of the IEEE 15th International Symposium on Personal, 2004

Dynamic image adaptation technique and architecture to enhance server performance in wireless image services.
Proceedings of the IEEE 15th International Symposium on Personal, 2004

Run-time allocation of buffer resources for maximizing video clip quality in a wireless last-hop system.
Proceedings of IEEE International Conference on Communications, 2004

VSHAPER: an efficient method of serving video streams shaped for diverse wireless communication conditions.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits.
Proceedings of the 41th Design Automation Conference, 2004

2003
High-level macro-modeling and estimation techniques for switching activity and power consumption.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Fault-coverage analysis techniques of crosstalk in chip interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects.
J. Electron. Test., 2003

High-level Synthesis of Multi-process Behavioral Descriptions.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Noise-Aware Driver Modeling for Nanometer Technology.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Separate Dual-Transistor Registers - A Circuit Solution for On-line Testing of Transient Error in UDSM-IC.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Dynamic Platform Management for Configurable Platform-Based System-on-Chips.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Software-based self-test methodology for crosstalk faults in processors.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Addressing Server Latency and Capacity to Enable Fast and Affordable Wireless Image Data Services.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

A scalable software-based self-test methodology for programmable processors.
Proceedings of the 40th Design Automation Conference, 2003

2002
Cosimulation-based power estimation for system-on-chip design.
IEEE Trans. Very Large Scale Integr. Syst., 2002

An Interconnect Architecture for Networking Systems on Chips.
IEEE Micro, 2002

Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores.
J. Electron. Test., 2002

Communication-Based Power Management.
IEEE Des. Test Comput., 2002

Embedded Software-Based Self-Test for Programmable Core-Based Designs.
IEEE Des. Test Comput., 2002

Validation and Test of Network Processors and ASICs.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract).
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Adaptive and energy efficient wavelet image compression for mobile multimedia data services.
Proceedings of the IEEE International Conference on Communications, 2002

Battery-efficient architecture for an 802.11 MAC processor.
Proceedings of the IEEE International Conference on Communications, 2002

Communication architecture based power management for battery efficient system design.
Proceedings of the 39th Design Automation Conference, 2002

Embedded software-based self-testing for SoC design.
Proceedings of the 39th Design Automation Conference, 2002

Software-based diagnosis for processors.
Proceedings of the 39th Design Automation Conference, 2002

Fast system-level power profiling for battery-efficient system design.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
System-level performance analysis for designing on-chipcommunication architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Software-based self-testing methodology for processor cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

High-level Crosstalk Defect Simulation for System-on-Chip Interconnects.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Battery Life Estimation of Mobile Embedded Systems.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Adaptive image compression for wireless multimedia communication.
Proceedings of the IEEE International Conference on Communications, 2001

Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies.
Proceedings of the 38th Design Automation Conference, 2001

On-Chip Communication Architecture for OC-768 Network Processors.
Proceedings of the 38th Design Automation Conference, 2001

2000
A fast and low-cost testing technique for core-based system-chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Using a Soft Core in a SoC Design: Experiences with picoJava.
IEEE Des. Test Comput., 2000

DEFUSE: A Deterministic Functional Self-Test Methodology for Processors.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Performance Analysis of Systems with Multi-Channel Communication Architectures.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Analysis of interconnect crosstalk defect coverage of test sets.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Test of Future System-on-Chips.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Efficient Exploration of the SoC Communication Architecture Design Space.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Interface based hardware/software validation of a system-on-chip.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

Efficient Power Co-Estimation Techniques for System-on-Chip Design.
Proceedings of the 2000 Design, 2000

Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips.
Proceedings of the 37th Conference on Design Automation, 2000

Test challenges for deep sub-micron technologies.
Proceedings of the 37th Conference on Design Automation, 2000

Embedded hardware and software self-testing methodologies for processor cores.
Proceedings of the 37th Conference on Design Automation, 2000

Self-test methodology for at-speed test of crosstalk in chip interconnects.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Power management in high-level synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Register transfer level power optimization with emphasis on glitch analysis and reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

A low overhead design for testability and test generation technique for core-based systems-on-a-chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Controller-based power management for control-flow intensive designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Resynthesis and retiming for optimum partial scan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Testing Embedded-Core-Based System Chips.
Computer, 1999

Low Power Design Methodologies for Systems-on-Chips.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Fast performance analysis of bus-based system-on-chip communication architectures.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Fault modeling and simulation for crosstalk in system-on-chip interconnects.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Common-Case Computation: A High-Level Technique for Power and Performance Optimization.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization.
ACM Trans. Design Autom. Electr. Syst., 1998

A controller redesign technique to enhance testability of controller-data path circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits.
J. Electron. Test., 1998

Design for Testability Techniques at the Behavioral and Register-Transfer Levels.
J. Electron. Test., 1998

A Power Management Methodology for High-Level Synthesis.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Transforming control-flow intensive designs to facilitate power management.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

High-level design validation and test.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

A Fast and Low Cost Testing Technique for Core-Based System-on-Chip.
Proceedings of the 35th Conference on Design Automation, 1998

A case study on modeling shared memory access effects during performance analysis of HW/SW systems.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

Considering Testability during High-level Design (Embedded Tutorial).
Proceedings of the ASP-DAC '98, 1998

High-Level Power Analysis and Optimization.
Kluwer, ISBN: 978-0-7923-8073-3, 1998

1997
Nonscan design-for-testability techniques using RT-level design information.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Performance analysis of a system of communicating processes.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

An RTL methodology to enable low overhead combinational testing.
Proceedings of the European Design and Test Conference, 1997

Power Management Techniques for Control-Flow Intensive Designs.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Fast true delay estimation during high level synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Controller re-specification to minimize switching activity in controller/data path circuits.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Register-transfer level estimation techniques for switching activity and power consumption.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

High-Level Synthesis for Testability: A Survey and Perspective.
Proceedings of the 33st Conference on Design Automation, 1996

Glitch Analysis and Reduction in Register Transfer Level.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Exploiting multicycle false paths in the performance optimization of sequential logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Design of testable sequential circuits by repositioning flip-flops.
J. Electron. Test., 1995

Design-for-debugging of application specific designs.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

A controller-based design-for-testability technique for controller-data path circuits.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Synthesis-for-testability using transformations.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Retiming sequential circuits to enhance testability.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Non-scan design-for-testability of RT-level data paths.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Provably correct high-level timing analysis without path sensitization.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Behavioral synthesis of low-cost partial scan designs for DSP applications.
Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994

Optimizing Resource Utilization and Testability Using Hot Potato Techniques.
Proceedings of the 31st Conference on Design Automation, 1994

Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications.
Proceedings of the 31st Conference on Design Automation, 1994

Clock Period Optimization During Resource Sharing and Assignment.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Transformations and resynthesis for testability of RT-level control-data path specifications.
IEEE Trans. Very Large Scale Integr. Syst., 1993

High Performance Embedded System Optimization Using Algebraic and Generalized Retiming Techniques.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Exploiting hardware sharing in high-level synthesis for partial scan optimization.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Critical Path Minimization Using Retiming and Algebraic Speed-Up.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Sequential Circuit Delay optimization Using Global Path Delays.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Performance optimization of sequential circuits by eliminating retiming bottlenecks.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Exploiting multi-cycle false paths in the performance optimization of sequential circuits.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991
Identification and Resynthesis of Pipelines in Sequential Networks.
Proceedings of the VLSI 91, 1991

Partitioning Sequential Circuits for Logic Optimization.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990
A New Parallel Sorting Algorithm and its Efficient VLSI Implementation.
Comput. J., 1990

Corolla Based Circuit Partitioning and Resynthesis.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1988
Parallel VLSI computation of all shortest paths in a graph.
Proceedings of the Sixteenth ACM Annual Conference on Computer Science, 1988


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