Sujal Vora

According to our database, Sujal Vora authored at least 5 papers between 2006 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

SkyLake-SP: A 14nm 28-Core xeon® processor.

Simon M. Tam, Harry Muljono, Min Huang, Sitaraman Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, Sujal Vora, Eddie Wang

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2014

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family.

Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

Innovative practices session 10C: Delay test.

P. Pant, M. Amodeo, Sujal Vora, Jonathon E. Colburn

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2009

Power reduction techniques for an 8-core xeon® processor.

Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2006

Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache.

Simon Tam, Justin Leung, Rahul Dilip Limaye, Sam Choy, Sujal Vora, Mitsuhiro Adachi

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006