Suhas Shivapakash

Orcid: 0000-0002-9173-213X

According to our database¹, Suhas Shivapakash authored at least 4 papers between 2020 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

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2024

Energy efficient hardware architectures for memory prohibitive deep neural networks.

[BibT_eX]

[DOI]

Suhas Shivapakash

PhD thesis, 2024

2021

FantastIC4: A Hardware-Software Co-Design Approach for Efficiently Running 4Bit-Compact Multilayer Perceptrons.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2021

A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2021

2020

A Power Efficient Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Suhas Shivapakash

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