Suhaib A. Fahmy

Jason D. Bakos

ACM Trans. Reconfigurable Technol. Syst., September, 2024

Collaborative Learning at the Edge for Air Pollution Prediction.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2024

ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips.

[BibT_eX]

[DOI]

Ahmad T. Sheikh

Ali Shoker

Paulo Jorge Esteves Veríssimo

CoRR, 2024

Resilient and Secure Programmable System-on-Chip Accelerator Offload.

[BibT_eX]

[DOI]

Paulo Jorge Esteves Veríssimo

CoRR, 2024

The NAIL Accelerator Interface Layer for Low Latency FPGA Offload.

[BibT_eX]

[DOI]

Nidhin Thandassery Sumithran

IEEE Access, 2024

SqueezeNIC: Low-Latency In-NIC Compression for Distributed Deep Learning.

[BibT_eX]

[DOI]

Achref Rebai

Mubarak Adetunji Ojewale

Anees Ullah

Marco Canini

Proceedings of the 2024 SIGCOMM Workshop on Networks for AI Computing, 2024

Low-Cost SCADA/HMI with Tiny Machine Learning for Monitoring Indoor CO2 Concentration.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2024

High Throughput Massive MIMO Signal Decoding Using Multi-Level Tree Search on FPGAs.

[BibT_eX]

[DOI]

Mohamed W. Hassan

Hatem Ltaief

Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024

Split DNN Inference for Exploiting Near-Edge Accelerators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Edge Computing and Communications, 2024

DONNA: Distributed Optimized Neural Network Allocation on CIM-Based Heterogeneous Accelerators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Edge Computing and Communications, 2024

Leveraging MLIR for Efficient Irregular-Shaped CGRA Overlay Design: (PhD Forum Paper).

[BibT_eX]

[DOI]

Mohamed Bouaziz

Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023

ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., September, 2023

Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs.

[BibT_eX]

[DOI]

Nidhin Thandassery Sumithran

ACM Trans. Reconfigurable Technol. Syst., March, 2023

Signal Detection for Large MIMO Systems Using Sphere Decoding on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Introducing the NAIL Accelerator Interface Layer for Low Latency FPGA Offload.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Technology, 2023

Exploring FPGA Acceleration for Distributed Serverless Computing.

[BibT_eX]

[DOI]

Ziyi Yang

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

REFL: Resource-Efficient Federated Learning.

[BibT_eX]

[DOI]

Proceedings of the Eighteenth European Conference on Computer Systems, 2023

2022

Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2022

Correction to: Estimation of missing air pollutant data using a spatiotemporal convolutional autoencoder.

[BibT_eX]

[DOI]

Neural Comput. Appl., 2022

Estimation of missing air pollutant data using a spatiotemporal convolutional autoencoder.

[BibT_eX]

[DOI]

Neural Comput. Appl., 2022

High Throughput Multidimensional Tridiagonal Systems Solvers on FPGAs.

[BibT_eX]

[DOI]

CoRR, 2022

FPGA Acceleration of Structured-Mesh-Based Explicit and Implicit Numerical Solvers using SYCL.

[BibT_eX]

[DOI]

Proceedings of the IWOCL'22: International Workshop on OpenCL, Bristol, United Kingdom, May 10, 2022

High throughput multidimensional tridiagonal system solvers on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022

2021

Optimum Battery Weight for Maximizing Available Energy in UAV-Enabled Wireless Communications.

[BibT_eX]

[DOI]

IEEE Wirel. Commun. Lett., 2021

Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs.

[BibT_eX]

[DOI]

Kalindu Herath

Alok Prakash

Thambipillai Srikanthan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Optimising Deep Learning at the Edge for Accurate Hourly Air Quality Prediction.

[BibT_eX]

[DOI]

Sensors, 2021

Resource-Efficient Federated Learning.

[BibT_eX]

[DOI]

CoRR, 2021

High-Level FPGA Accelerator Design for Structured-Mesh-Based Explicit Numerical Solvers.

[BibT_eX]

[DOI]

Richard P. Smedley-Stevenson

Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

StressBench: A Configurable Full System Network and I/O Benchmark Framework.

[BibT_eX]

[DOI]

Gihan R. Mudalidge

Stephen A. Jarvis

Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021

Heterogeneous Communication Virtualization for Distributed Embedded Applications.

[BibT_eX]

[DOI]

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Runtime Abstraction for Autonomous Adaptive Systems on Reconfigurable Hardware.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Toward Secure VMs Allocation: Analysis of VMs Allocation Behaviours in the Cloud Computing Environments.

[BibT_eX]

[DOI]

Mansour Aldawood

Arshad Jhumka

Proceedings of the Cloud Computing and Services Science - 11th International Conference, 2021

Sit Here: Placing Virtual Machines Securely in Cloud Environments.

[BibT_eX]

[DOI]

Mansour Aldawood

Arshad Jhumka

Proceedings of the 11th International Conference on Cloud Computing and Services Science, 2021

2020

High Throughput Spatial Convolution Filters on FPGAs.

[BibT_eX]

[DOI]

Abdullah Al-Dujaili

IEEE Trans. Very Large Scale Integr. Syst., 2020

Exploring hardware accelerator offload for the Internet of Things.

[BibT_eX]

[DOI]

it Inf. Technol., 2020

A model for distributed in-network and near-edge computing with heterogeneous hardware.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2020

High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Build Automation and Runtime Abstraction for Partial Reconfiguration on Xilinx Zynq UltraScale+.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2020

Characterizing Latency Overheads in the Deployment of FPGA Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Quantifying the latency benefits of near-edge and in-network FPGA acceleration.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Workshop on Edge Systems, Analytics and Networking, 2020

2019

The Power-optimised Software Envelope.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2019

Lightweight Programmable DSP Block Overlay for Streaming Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

Network Enabled Partial Reconfiguration for Distributed FPGA Edge Acceleration.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

Neural Network Overlay Using FPGA DSP Blocks.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Network Intrusion Detection Using Neural Networks on FPGA SoCs.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018

Efficient Spectrum Sensing for Aeronautical LDACS Using Low-Power Correlators.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Smart Network Interfaces for Advanced Automotive Applications.

[BibT_eX]

[DOI]

IEEE Micro, 2018

FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2018

A Smart Network Interface Approach for Distributed Applications on Xilinx Zynq SoCs.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A time-multiplexed FPGA overlay with linear interconnect.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Design Abstraction for Autonomous Adaptive Hardware Systems on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

2017

Security in Automotive Networks: Lightweight Authentication and Authorization.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

Multipumping Flexible DSP Blocks for Resource Reduction on Xilinx FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

VEGa: A High Performance Vehicular Ethernet Gateway on Hybrid FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Fracturable DSP Block for Multi-context Reconfigurable Architectures.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2017

High Throughput 2D Spatial Image Filters on FPGAs.

[BibT_eX]

[DOI]

Abdullah Al-Dujaili

CoRR, 2017

Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays.

[BibT_eX]

[DOI]

CoRR, 2017

An End-to-End Multi-Standard OFDM Transceiver Architecture Using FPGA Partial Reconfiguration.

[BibT_eX]

[DOI]

IEEE Access, 2017

Virtualized Execution Runtime for FPGA Accelerators in the Cloud.

[BibT_eX]

[DOI]

IEEE Access, 2017

Metrics for Energy-Aware Software Optimisation.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing - 32nd International Conference, 2017

In-network online data analytics with FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

Efficient Integer Frequency Offset Estimation Architecture for Enhanced OFDM Synchronization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Design and Realization of Variable Digital Filters for Software-Defined Radio Channelizers Using an Improved Coefficient Decimation Method.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Mapping for Maximum Performance on FPGA DSP Blocks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Open source model and simulator for real-time performance analysis of automotive network security.

[BibT_eX]

[DOI]

SIGBED Rev., 2016

Spectrally efficient emission mask shaping for OFDM cognitive radios.

[BibT_eX]

[DOI]

Digit. Signal Process., 2016

An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units.

[BibT_eX]

[DOI]

CoRR, 2016

JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Improved resource sharing for FPGA DSP blocks.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Designing a virtual runtime for FPGA accelerators in the cloud.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Initiation Interval Aware Resource Sharing for FPGA DSP Blocks.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Accelerated Artificial Neural Networks on FPGA for fault detection in automotive systems.

[BibT_eX]

[DOI]

Bezborah Anshuman

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Throughput oriented FPGA overlays using DSP blocks.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE 14th Intl Conf on Dependable, 2016

Message from the ASAP 2016 chairs.

[BibT_eX]

[DOI]

David Thomas

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015

Extensible FlexRay Communication Controller for FPGA-Based Automotive Systems.

[BibT_eX]

[DOI]

IEEE Trans. Veh. Technol., 2015

Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2015

JIT trace-based verification for high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Minimizing DSP block usage through multi-pumping.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

On Data Forwarding in Deeply Pipelined Soft Processors.

[BibT_eX]

[DOI]

Nachiket Kapre

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Efficient Overlay Architecture Based on DSP Blocks.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Lightweight authentication for secure automotive networks.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Security aware network controllers for next generation automotive embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Security analysis of automotive architectures using probabilistic model checking.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Dynamic Cognitive Radios on the Xilinx Zynq Hybrid FPGA.

[BibT_eX]

[DOI]

Proceedings of the Cognitive Radio Oriented Wireless Networks, 2015

Virtualized FPGA Accelerators for Efficient Cloud Computing.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International Conference on Cloud Computing Technology and Science, 2015

Mapping adaptive hardware systems with partial reconfiguration using CoPR for Zynq.

[BibT_eX]

[DOI]

Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014

Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2014

The iDEA DSP Block-Based Soft Processor for FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2014

ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2014

Robust and Efficient OFDM Synchronization for FPGA-Based Radios.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2014

Shaping Spectral Leakage for IEEE 802.11p Vehicular Communications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 79th Vehicular Technology Conference, 2014

A case for leveraging 802.11p for direct phone-to-phone communications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

System simulation and optimization using reconfigurable hardware.

[BibT_eX]

[DOI]

Martin Lukasiewycz

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Zero latency encryption with FPGAs for secure time-triggered automotive networks.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Analysis and optimization of a deeply pipelined FPGA soft processor.

[BibT_eX]

[DOI]

Nachiket Kapre

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

DyRACT: A partial reconfiguration enabled accelerator and test platform.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Efficient mapping of mathematical expressions into DSP blocks.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Efficient multi-standard cognitive radios on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Square-rich fixed point polynomial evaluation on FPGAs.

[BibT_eX]

[DOI]

Simin Xu

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Automated Partial Reconfiguration Design for Adaptive Systems with CoPR for Zynq.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Experiments in Mapping Expressions to DSP Blocks.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Mapping Time-Critical Safety-Critical Cyber Physical Systems to Hybrid FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Cyber-Physical Systems, 2014

A scalable and compact systolic architecture for linear solvers.

[BibT_eX]

[DOI]

Kevin Shen-Hoong Ong

Keck Voon Ling

Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013

Low-Power Correlation for IEEE 802.16 OFDM Synchronization on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Architecture for Real-Time Nonparametric Probability Density Function Estimation.

[BibT_eX]

[DOI]

A. R. Mohan

IEEE Trans. Very Large Scale Integr. Syst., 2013

Reconfigurable Computing in Next-Generation Automotive Networks.

[BibT_eX]

[DOI]

Martin Lukasiewycz

IEEE Embed. Syst. Lett., 2013

Optimization of the HEFT Algorithm for a CPU-GPU Environment.

[BibT_eX]

[DOI]

Karan R. Shetti

Timo Bretschneider

Proceedings of the International Conference on Parallel and Distributed Computing, 2013

Automated Partitioning for Partial Reconfiguration Design of Adaptive Systems.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

System-level FPGA device driver with high-level synthesis support.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Accelerating validation of time-triggered automotive systems on FPGAs.

[BibT_eX]

[DOI]

Martin Lukasiewycz

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Enhancing communication on automotive networks using data layer extensions.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Iterative floating point computation using FPGA DSP blocks.

[BibT_eX]

[DOI]

Fredrik Brosser

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Efficient Large Integer Squarers on FPGA.

[BibT_eX]

[DOI]

Simin Xu

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

An Approach to a Fully Automated Partial Reconfiguration Design Flow.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

An approach for redundancy in FlexRay networks using FPGA partial reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

System architecture and software design for electric vehicles.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Microkernel hypervisor for a hybrid ARM-FPGA platform.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012

A high speed open source controller for FPGA Partial Reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

iDEA: A DSP block based FPGA soft processor.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Evaluating the efficiency of DSP Block synthesis inference from flow graphs.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A lean FPGA soft processor built using a DSP block.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Embedded systems and software challenges in electric vehicles.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

A Model-Based Approach to Cognitive Radio Design.

[BibT_eX]

[DOI]

IEEE J. Sel. Areas Commun., 2011

Efficient region allocation for adaptive partial reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

A threat-based Connect6 implementation on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Enabling high level design of adaptive systems with partial reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

2010

Iris: an architecture for cognitive radio networking testbeds.

[BibT_eX]

[DOI]

IEEE Commun. Mag., 2010

Histogram-based probability density function estimation on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

Multi-platform demonstrations using the Iris architecture for cognitive radio network testbeds.

[BibT_eX]

[DOI]

Proceedings of the 5th International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2010

Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing.

[BibT_eX]

[DOI]

Linda Doyle

Proceedings of the Reconfigurable Computing: Architectures, 2010

2009

High-throughput one-dimensional median and weighted median filters on FPGA.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2009

Development Framework for Implementing FPGA-Based Cognitive Network Nodes.

[BibT_eX]

[DOI]

Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

Generic Software Framework for Adaptive Applications on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the FCCM 2009, 2009

2008

Hardware acceleration of the trace transform for vision applications.

[BibT_eX]

[DOI]

Suhaib Ahmed Fahmy

PhD thesis, 2008

Generalised Parallel Bilinear Interpolation Architecture for Vision Systems.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

2007

Real-time hardware acceleration of the trace transform.

[BibT_eX]

[DOI]

Christos-Savvas Bouganis

J. Real Time Image Process., 2007

2006

Efficient Realtime FPGA Implementation of the Trace Transform.

[BibT_eX]

[DOI]

Christos-Savvas Bouganis

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Investigating Trace Transform Architectures for Face Authentication.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005

Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Hardware Acceleration of Hidden Markov Model Decoding for Person Detection.

[BibT_eX]

[DOI]