Sudhakar Surendran

Orcid: 0009-0005-9277-4314

According to our database1, Sudhakar Surendran authored at least 7 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

2008
2010
2012
2014
2016
2018
2020
2022
2024
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Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
MAB-BMC: A Formal Verification Enhancer by Harnessing Multiple BMC Engines Together.
ACM Trans. Design Autom. Electr. Syst., 2024

2023
Analog Coverage-driven Selection of Simulation Corners for AMS Integrated Circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
The CoveRT Approach for Coverage Management in Analog and Mixed-Signal Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Tracking Coverage Artefacts for Periodic Signals using Sequence-based Abstractions.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

2020
CoveRT: A Coverage Reporting Tool for Analog Mixed-Signal Designs.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

The Notion of Cross Coverage in AMS Design Verification.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2008
A systematic approach to synthesis of verification test-suites for modular SoC designs.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008


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