Sudhakar Pamarti

Orcid: 0000-0003-1457-7508

According to our database1, Sudhakar Pamarti authored at least 98 papers between 2003 and 2024.

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Bibliography

2024
SCIMITAR: Stochastic Computing In-Memory In-Situ Tracking ARchitecture for Event-Based Cameras.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024

Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation.
IEEE J. Solid State Circuits, October, 2024

Digital Residual Alias Cancellation for Filtering-by-Aliasing Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

FPGA Crystal Oscillator Circuit Emulation Based on Wave Digital Filter.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024

Voltage-Controlled Magnetoelectric Devices for Neuromorphic Diffusion Process.
CoRR, 2024

A 278-514M Event/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Cryogenic Alternative: CMOS Versus Dynamic-Based Logic.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Novel Energy-Efficient and Latency-Improved PVT Tolerant Read Scheme for SRAM Design in Video Processing and Machine Learning Applications.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

A Sub-Sampling 35GHz PLL in 45nm PDSOI BiCMOS with 37fs Integrated Jitter and a FoM of -252dB.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2024

2023
REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

A Spur-free Dynamic Element Matching Scheme for Bandpass DACs.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Analytical Array-Level Comparison of Read/Write Performance Between Voltage Controlled-MRAM and STT-MRAM.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022
A Dual-Channel High-Linearity Filtering-by-Aliasing Receiver Front-End Supporting Carrier Aggregation.
IEEE J. Solid State Circuits, 2022

A 14-bit 1-GS/s SiGe Bootstrap Sampler for High Resolution ADC with 250-MHz Input.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Digital Alias Cancellation Technique for Filtering-by-Aliasing Receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Periodically Time-Varying Noise Cancellation for Filtering-by-Aliasing Receiver Front Ends.
IEEE J. Solid State Circuits, 2021

Session 6 Overview: High-Performance Receivers and Transmitters for Sub-6GHz Radios Wireless Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

6.3 A 0.9V Dual-Channel Filtering-by-Aliasing Receiver Front-End Achieving +35dBm IIP3 and <-81dBm LO Leakage Supporting Intra-and Inter-Band Carrier Aggregation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS.
Proceedings of the 47th ESSCIRC 2021, 2021

GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Designing a 2048-Chiplet, 14336-Core Waferscale Processor.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2020

ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
A Sub-nW 32-kHz Crystal Oscillator Architecture Based on a DC-Only Sustaining Amplifier.
IEEE J. Solid State Circuits, 2019

A 0.5-to-2.5GHz Multi-Output Fractional Frequency Synthesizer with 90fs Jitter and -106dBc Spurious Tones Based on Digital Spur Cancellation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 0.55nW/0.5V 32kHz Crystal Oscillator Based on a DC-Only Sustaining Amplifier for IoT.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

An 8.5pJ/bit Ultra-Low Power Wake-Up Receiver Using Schottky Diodes for IoT Applications.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

An LPTV Noise Cancellation Technique for a 0.9-V Filtering-by-Aliasing Receiver Front-End with >67-dB Stopband Rejection.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
Theoretical Analysis of Circuit Non-Idealities in a Passive Spectrum Scanner Based on Periodically Time-Varying Circuit Components.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Impedance Matching and Reradiation in LPTV Receiver Front-Ends: An Analysis Using Conversion Matrices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Broadband Class-AB Power Amplifier With Instantaneous Supply-Switching Efficiency Enhancement for Cable TV Application.
IEEE J. Solid State Circuits, 2018

Design and Analysis of a Programmable Receiver Front End With Time-Interleaved Baseband Analog-FIR Filtering.
IEEE J. Solid State Circuits, 2018

Errata for "Design and Analysis of a Programmable Receiver Front End Based on Baseband Analog-FIR Filtering Using an LPTV Resistor".
IEEE J. Solid State Circuits, 2018

Design and Analysis of a Programmable Receiver Front End Based on Baseband Analog-FIR Filtering Using an LPTV Resistor.
IEEE J. Solid State Circuits, 2018

A Quick Startup Technique for High-Q Oscillators Using Precisely Timed Energy Injection.
IEEE J. Solid State Circuits, 2018

2017
High-Efficiency Millimeter-Wave Energy-Harvesting Systems With Milliwatt-Level Output Power.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With >+31 dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components.
IEEE J. Solid State Circuits, 2017

A MEMS-Assisted Temperature Sensor With 20-µK Resolution, Conversion Rate of 200 S/s, and FOM of 0.04 pJK2.
IEEE J. Solid State Circuits, 2017

A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology.
IEEE J. Solid State Circuits, 2017

24.6 A time-interleaved filtering-by-aliasing receiver front-end with >70dB suppression at <4× bandwidth frequency offset.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Session 3 - Clocking techniques.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 10-to-650MHz 1.35W class-AB power amplifier with instantaneous supply-switching efficiency enhancement.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A precisely-timed energy injection technique achieving 58/10/2μs start-up in 1.84/10/50MHz crystal oscillators.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Frequency-Domain Analysis of N-Path Filters Using Conversion Matrices.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

11.1 Dual-MEMS-resonator temperature-to-digital converter with 40 K resolution and FOM of 0.12pJK2.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

26.6 A programmable receiver front-end achieving >17dBm IIP3 at <1.25×BW frequency offset.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Time-varying circuit approaches for software defined and cognitive radio applications.
Proceedings of the International SoC Design Conference, 2016

Wave digital filter based analog circuit emulation on FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Linearization Through Dithering: A 50 MHz Bandwidth, 10-b ENOB, 8.2 mW VCO-Based ADC.
IEEE J. Solid State Circuits, 2015

A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator.
IEEE J. Solid State Circuits, 2015

A sharp programmable passive filter based on filtering by Aliasing.
Proceedings of the Symposium on VLSI Circuits, 2015

Frequency-domain analysis of a mixer-first receiver using conversion matrices.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014
RF digital predistorter implementation using polynomial optimization.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

23.8 A 34V charge pump in 65nm bulk CMOS technology.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

12.9 A 1.55×0.85mm<sup>2</sup> 3ppm 1.0μA 32.768kHz MEMS-based oscillator.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
Filtering by Aliasing.
IEEE Trans. Signal Process., 2013

A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With < ±0.5-ppm Frequency Stability and < 1-ps Integrated Jitter.
IEEE J. Solid State Circuits, 2013

Enabling high-speed, high-resolution ADCs using signal conditioning algorithms.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Mitigating timing errors in time-interleaved ADCs: A signal conditioning approach.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Adaptive signal conditioning algorithms to enable wideband signal digitization.
Proceedings of IEEE International Conference on Communications, 2013

Filtering of subtractive discrete dither in quantizers: Some new results.
Proceedings of the IEEE International Conference on Acoustics, 2013

A 50MHz bandwidth, 10-b ENOB, 8.2mW VCO-based ADC enabled by filtered-dithering based linearization.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Clock/Frequency Generation Circuits and Systems.
J. Electr. Comput. Eng., 2012

Dithered quantizers with negligible in-band dither power
CoRR, 2012

A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stability.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Robustness of xampling-based RF receivers against analog mismatches.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

2011
A Spur-Free MASH DDSM With High-Order Filtered Dither.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 2.4 GHz Wideband Open-Loop GFSK Transmitter With Phase Quantization Noise Cancellation.
IEEE J. Solid State Circuits, 2011

Open-Loop Wide-Bandwidth Phase Modulation Techniques.
J. Electr. Comput. Eng., 2011

A novel reconfigurable alias interference cancellation technique for A-to-D conversion.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A progammable baseband anti-alias filter for a passive-mixer-based, SAW-less, multi-band, multi-mode WEDGE transmitter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Mismatch Shaping Techniques to Linearize Charge Pump Errors in Fractional-N PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A Digital Envelope Combiner for Switching Power Amplifier Linearization.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator.
IEEE J. Solid State Circuits, 2010

A 3 , ˟, 3.8 Gb/s Four-Wire High Speed I/O Link Based on CDMA-Like Crosstalk Cancellation.
IEEE J. Solid State Circuits, 2010

A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A power amplifier with minimal efficiency degradation under back-off.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 16 Gb/s four-wire CDMA-based high speed I/O link with transmitter timing adjustment.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Fractional-N Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Digital techniques for integrated frequency synthesizers: A tutorial.
IEEE Commun. Mag., 2009

Worst case timing jitter and amplitude noise in differential signaling.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Joint design-time and post-silicon optimization for digitally tuned analog circuits.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A 3×3.8Gb/s four-wire high speed I/O link based on CDMA-like crosstalk cancellation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
A Spur Elimination Technique for Phase Interpolation-Based Fractional-N PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A Theoretical Study of the Quantization Noise in Split Delta-Sigma ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

The Effect of Noise Cross-Coupling on Time-Interleaved Delta-Sigma ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

2007
Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta-Sigma Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

LSB Dithering in MASH Delta-Sigma D/A Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

A Theoretical Analysis of Split Delta-Sigma ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Replica compensated linear regulators for supply-regulated phase-locked loops.
IEEE J. Solid State Circuits, 2006

Power-efficient pulse width modulation DC/DC converters with zero voltage switching control.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2005
Addition to "A Wideband 2.4-GHz Delta-Sigma Fractional-$N$PLL With 1-Mb/s In-Loop Modulation".
IEEE J. Solid State Circuits, 2005

2004
A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation.
IEEE J. Solid State Circuits, 2004

2003
Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs.
IEEE Trans. Circuits Syst. II Express Briefs, 2003


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