Sudhakar M. Reddy
Orcid: 0000-0001-9208-8262Affiliations:
- University of Iowa, Iowa City, IA, USA
According to our database1,
Sudhakar M. Reddy
authored at least 638 papers
between 1968 and 2022.
Collaborative distances:
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Bibliography
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IET Comput. Digit. Tech., 2020
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations.
Proceedings of the IEEE International Test Conference, 2020
Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels.
Proceedings of the IEEE International Test Conference in Asia, 2020
Proceedings of the IEEE European Test Symposium, 2020
2019
An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design.
ACM Trans. Design Autom. Electr. Syst., 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 28th IEEE Asian Test Symposium, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the IEEE International Test Conference, 2018
Proceedings of the IEEE International Test Conference, 2018
Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run.
Proceedings of the IEEE International Test Conference in Asia, 2018
Proceedings of the 23rd IEEE European Test Symposium, 2018
2017
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the International Test Conference in Asia, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data.
Proceedings of the 26th IEEE Asian Test Symposium, 2017
2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits.
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 2015 IEEE International Test Conference, 2015
2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
Fundamentals of Small-Delay Defect Testing.
Proceedings of the Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., 2014
2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the 22nd Asian Test Symposium, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IET Comput. Digit. Tech., 2012
Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation.
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
ACM Trans. Design Autom. Electr. Syst., 2011
IEEE Trans. Dependable Secur. Comput., 2011
J. Low Power Electron., 2011
Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation.
IET Comput. Digit. Tech., 2011
IET Comput. Digit. Tech., 2011
IET Comput. Digit. Tech., 2011
Proceedings of the 2011 IEEE International Test Conference, 2011
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis.
IEEE Trans. Computers, 2010
J. Low Power Electron., 2010
Int. J. Parallel Program., 2010
IET Comput. Digit. Tech., 2010
IET Comput. Digit. Tech., 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Selecting state variables for improved on-line testability through output response comparison of identical circuits.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 15th European Test Symposium, 2010
Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits.
ACM Trans. Design Autom. Electr. Syst., 2009
Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits.
IEEE Trans. Dependable Secur. Comput., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IET Comput. Digit. Tech., 2009
IET Comput. Digit. Tech., 2009
Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution.
IET Comput. Digit. Tech., 2009
IET Comput. Digit. Tech., 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation.
Proceedings of the 14th IEEE European Test Symposium, 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Improving compressed test pattern generation for multiple scan chain failure diagnosis.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Dynamic test compaction for a random test generation procedure with input cube avoidance.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion.
IEEE Trans. Very Large Scale Integr. Syst., 2008
Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects.
IEEE Trans. Very Large Scale Integr. Syst., 2008
On the Saturation of n-Detection Test Generation by Different Definitions With Increased n.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
J. Low Power Electron., 2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
ACM Trans. Design Autom. Electr. Syst., 2007
Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints.
ACM Trans. Design Autom. Electr. Syst., 2007
z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IET Comput. Digit. Tech., 2007
IET Comput. Digit. Tech., 2007
Worst-case and average-case analysis of n-detection test sets and test generation strategies.
IET Comput. Digit. Tech., 2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Faster defect localization in nanometer technology based on defective cell diagnosis.
Proceedings of the 2007 IEEE International Test Conference, 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 12th European Test Symposium, 2007
Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 16th Asian Test Symposium, 2007
Proceedings of the 16th Asian Test Symposium, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Scan-BIST based on transition probabilities for circuits with single and multiple scan chains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan.
IEEE Trans. Computers, 2006
On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits.
Proceedings of the Workshop on Verification and Debugging, 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the 2006 IEEE International Test Conference, 2006
Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences.
Proceedings of the 2006 IEEE International Test Conference, 2006
A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 15th Asian Test Symposium, 2006
Proceedings of the 15th Asian Test Symposium, 2006
A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops.
Proceedings of the 15th Asian Test Symposium, 2006
Cache size selection for performance, energy and reliability of time-constrained systems.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Dependable Secur. Comput., 2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
On masking of redundant faults in synchronous sequential circuits with design-for-testability logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
On reducing test application time for scan circuits using limited scan operations and transfer sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 10th European Test Symposium, 2005
Proceedings of the 10th European Test Symposium, 2005
A unified fault model and test generation procedure for interconnect opens and bridges.
Proceedings of the 10th European Test Symposium, 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
2004
Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations.
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests.
IEEE Trans. Computers, 2004
On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit.
IEEE Trans. Computers, 2004
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units.
IEEE Trans. Computers, 2004
IEICE Trans. Inf. Syst., 2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values.
Proceedings of the 9th European Test Symposium, 2004
Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
2003
ACM Trans. Design Autom. Electr. Syst., 2003
Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Reverse-order-restoration-based static test compaction for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Proceedings of the VLSI-SOC: From Systems to Chips, 2003
On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
On path selection for delay fault testing considering operating conditions [logic IC testing].
Proceedings of the 8th European Test Workshop, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set.
IEEE Trans. Computers, 2002
Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission.
IEEE Trans. Computers, 2002
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times.
IEEE Trans. Computers, 2002
J. Electron. Test., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Properties of Output Sequences and their Use in Guiding Property-Based Test Generation for Synchronous Sequential Circuits.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units.
IEEE Trans. Very Large Scale Integr. Syst., 2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Vector replacement to improve static-test compaction forsynchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits.
J. Syst. Archit., 2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
A method to enhance the fault coverage obtained by output response comparison of identical circuits.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001
ITEM: an iterative improvement test generation procedure for synchronous sequential circuits.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Sequence reordering to improve the levels of compaction achievable by static compaction procedures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits.
IEEE Trans. Computers, 2000
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits.
IEEE Trans. Computers, 2000
On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines.
IEEE Trans. Computers, 2000
J. Electron. Test., 2000
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits.
Proceedings of the 5th European Test Workshop, 2000
Proceedings of the 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 2000
Proceedings of the 2000 Design, 2000
Proceedings of the 2000 Design, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Reducing test application time for full scan circuits by the addition of transfer sequences.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
Static test compaction for synchronous sequential circuits based on vector restoration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
A comment on "Improving a nonenumerative method to estimate path delay fault coverage".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits.
IEEE Trans. Computers, 1999
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
On achieving complete coverage of delay faults in full scan circuits using locally available lines.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits.
Proceedings of the IEEE International Conference On Computer Design, 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
Proceedings of the 4th European Test Workshop, 1999
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences.
Proceedings of the 36th Conference on Design Automation, 1999
Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction.
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
ACM Trans. Design Autom. Electr. Syst., 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Design-for-testability for path delay faults in large combinational circuits using test points.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Techniques for minimizing power dissipation in scan and combinational circuits during test application.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
IEEE Trans. Computers, 1998
Vertex Splitting in Dags and Applications to Partial Scan Designs and Lossy Circuits.
Int. J. Found. Comput. Sci., 1998
Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Improved built-in test pattern generators based on comparison units for synchronous sequential circuits.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
Proceedings of the Digest of Papers: FTCS-28, 1998
Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines.
Proceedings of the 1998 Design, 1998
Proceedings of the 1998 Design, 1998
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration.
Proceedings of the 1998 Design, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits .
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
IEEE Trans. Computers, 1997
IEEE Trans. Computers, 1997
Future Gener. Comput. Syst., 1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997
ACTIV-LOCSTEP: A Test Generation Procedure Based on Logic Simulation and Fault Activation.
Proceedings of the Digest of Papers: FTCS-27, 1997
On the use of reset to increase the testability of interconnected finite-state machines.
Proceedings of the European Design and Test Conference, 1997
Proceedings of the European Design and Test Conference, 1997
Fault Simulation under the Multiple Observation Time Approach using Backward Implications.
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
1996
On the effectiveness of residue code checking for parallel two's complement multipliers.
IEEE Trans. Very Large Scale Integr. Syst., 1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits.
IEEE Trans. Computers, 1996
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences.
IEEE Trans. Computers, 1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996
Proceedings of the High-Performance Computing and Networking, 1996
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996
Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques.
Proceedings of the Digest of Papers: FTCS-26, 1996
On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem.
Proceedings of the 1996 European Design and Test Conference, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
Proceedings of the 33st Conference on Design Automation, 1996
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996
On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996
1995
NEST: a nonenumerative test generation method for path delay faults in combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing.
IEEE Trans. Computers, 1995
IEEE Trans. Computers, 1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
Proceedings of the Proceedings EURO-DAC'95, 1995
Proceedings of the 32st Conference on Design Automation, 1995
Proceedings of the 32st Conference on Design Automation, 1995
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995
1994
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
IEEE Trans. Computers, 1994
IEEE Trans. Computers, 1994
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994
On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Test Pattern Generation for Path Delay Faults in Synchronous Sequential Circuits Using Multiple Fast Clocks and Multiple Observations Times.
Proceedings of the Digest of Papers: FTCS/24, 1994
Proceedings of the Digest of Papers: FTCS/24, 1994
Proceedings of the 31st Conference on Design Automation, 1994
Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points.
Proceedings of the 31st Conference on Design Automation, 1994
1993
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
IEEE Trans. Computers, 1993
IEEE Trans. Computers, 1993
Proceedings of the Sixth International Conference on VLSI Design, 1993
Proceedings of the Sixth International Conference on VLSI Design, 1993
Proceedings of the Sixth International Conference on VLSI Design, 1993
Heuristics for the Placement of Flip-Flops in Partial Scan Designs and the Placement of Signal Boosters in Lossy Circuits.
Proceedings of the Sixth International Conference on VLSI Design, 1993
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Proceedings of the Digest of Papers: FTCS-23, 1993
Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity.
Proceedings of the Digest of Papers: FTCS-23, 1993
Proceedings of the Digest of Papers: FTCS-23, 1993
A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis.
Proceedings of the European Design Automation Conference 1993, 1993
NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits.
Proceedings of the 30th Design Automation Conference. Dallas, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
1992
IEEE Trans. Neural Networks, 1992
On the design of random pattern testable PLA based on weighted random pattern testing.
J. Electron. Test., 1992
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992
Proceedings of the Fifth International Conference on VLSI Design, 1992
COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992
A Divide-And-Conquer Approach to Test Generation for Large Synchronous Sequential Circuits.
Proceedings of the Digest of Papers: FTCS-22, 1992
Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability.
Proceedings of the Digest of Papers: FTCS-22, 1992
Proceedings of the conference on European design automation, 1992
Proceedings of the 29th Design Automation Conference, 1992
Proceedings of the 29th Design Automation Conference, 1992
1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991
Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991
Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991
Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times.
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991
On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model.
Proceedings of the 28th Design Automation Conference, 1991
1990
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990
IEEE Trans. Computers, 1990
IEEE Des. Test Comput., 1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990
Proceedings of the European Design Automation Conference, 1990
1989
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989
On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement.
IEEE Trans. Computers, 1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989
1988
Proceedings of the Proceedings International Test Conference 1988, 1988
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988
1987
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987
1986
IEEE Trans. Computers, 1986
On the Design of Random Pattern Testable PLAs.
Proceedings of the Proceedings International Test Conference 1986, 1986
1985
On the Design of Testable Domino PLAs.
Proceedings of the Proceedings International Test Conference 1985, 1985
Design and Analysis of Fault-Tolerant Multistage Interconnection Networks With Low Link Complexity.
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985
On Multipath Multistage Interconnection Networks.
Proceedings of the 5th International Conference on Distributed Computing Systems, 1985
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985
1984
A Diagnosis Algorithm for Distributed Computing Systems with Dynamic Failure and Repair.
IEEE Trans. Computers, 1984
On CMOS Totally Self-Checking Circuits.
Proceedings of the Proceedings International Test Conference 1984, 1984
A Class of Graphs for Fault-Tolerant Processor Interconnections.
Proceedings of the 4th International Conference on Distributed Computing Systems, 1984
A gate level model for CMOS combinational logic circuits with application to fault detection.
Proceedings of the 21st Design Automation Conference, 1984
1983
On Testable Design for CMOS Logic Circuits.
Proceedings of the Proceedings International Test Conference 1983, 1983
A Class of Graphs for Processor Interconnection.
Proceedings of the International Conference on Parallel Processing, 1983
1982
IEEE Trans. Computers, 1982
Design of Easily Testable Microprocessors : A Case Study.
Proceedings of the Proceedings International Test Conference 1982, 1982
1981
IEEE Trans. Computers, 1981
1980
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories.
IEEE Trans. Computers, 1980
Proceedings of the 7th Annual Symposium on Computer Architecture, 1980
1978
A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems.
IEEE Trans. Computers, 1978
A Multicode Single Transition-Time State Assignment for Asynchronous Sequential Machines.
IEEE Trans. Computers, 1978
1977
IEEE Trans. Computers, 1977
1976
Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes.
IEEE Trans. Computers, 1976
1975
IEEE Trans. Computers, 1975
1974
IEEE Trans. Inf. Theory, 1974
Easily Testable Cellular Realizations for the (Exactly P)-out-of n and (p or More)-out-of n Logic Functions.
IEEE Trans. Computers, 1974
IEEE Trans. Computers, 1974
1973
1972
IEEE Trans. Inf. Theory, 1972
IEEE Trans. Computers, 1972
Proceedings of the 13th Annual Symposium on Switching and Automata Theory, 1972
1971
1970
Inf. Control., May, 1970
1969
IEEE Trans. Inf. Theory, 1969
1968
Inf. Control., November, 1968
Inf. Control., October, 1968
Inf. Control., January, 1968