Sudha Ellison Mathe
Orcid: 0000-0003-2806-5407
According to our database1,
Sudha Ellison Mathe
authored at least 7 papers
between 2017 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Microprocess. Microsystems, 2024
IEEE Access, 2024
2021
A systematic literature review on prototyping with Arduino: Applications, challenges, advantages, and limitations.
Comput. Sci. Rev., 2021
2018
Design and Implementation of a Novel Bit-Parallel Systolic Multiplier Over GF(2<sup><i>m</i></sup>) for Irreducible Pentanomials.
J. Circuits Syst. Comput., 2018
Bit-parallel systolic multiplier over GF ( 2 m ) for irreducible trinomials with ASIC and FPGA implementations.
IET Circuits Devices Syst., 2018
2017
KSII Trans. Internet Inf. Syst., 2017