Sudeep Puligundla

According to our database, Sudeep Puligundla authored at least 5 papers between 2009 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC.

Bruce Querbach, Rahul Khanna, Sudeep Puligundla, David Blankenbeckler, Joseph Crop, Patrick Yin Chiang

IEEE Des. Test, 2016

2015

Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine.

Bruce Querbach, Tan Peter Yanyang, Lovelace Van, David Blankenbeckler, Rahul Khanna, Sudeep Puligundla, Patrick Chiang

Proceedings of the 2015 IEEE International Test Conference, 2015

2013

Comparison of hardware based and software based stress testing of memory IO interface.

Bruce Querbach, Sudeep Puligundla, Daniel Becerra, Zale T. Schoenborn, Patrick Chiang

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2010

Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery.

Sudeep Puligundla, Fulvio Spagna, Lidong Chen, Amanda Tran

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

High speed I/O and thermal effect characterization of 3D stacked ICs.

Moishe Groger, Shadi M. Harb, Devin Morris, William R. Eisenstadt, Sudeep Puligundla

Proceedings of the IEEE International Conference on 3D System Integration, 2009