Sudeep Pasricha

IEEE Consumer Electron. Mag., 2019

Quality-Aware Voice Convergecast in Mobile Low Power Wireless Networks.

[BibT_eX]

[DOI]

Mike Adkins

Qi Han

Proceedings of the Mobile Computing, Applications, and Services, 2019

Message from the HCW General Chair.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

Introduction to HCW 2019.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

SHERPA: A Lightweight Smartphone Heterogeneity Resilient Portable Indoor Localization Framework.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

SLAM: High Performance and Energy Efficient Hybrid Last Level Cache Architecture for Multicore Embedded Systems.

[BibT_eX]

[DOI]

Swapnil Bhosale

Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

Green Computing with Geo-Distributed Heterogeneous Data Centers.

[BibT_eX]

[DOI]

Ninad Hogade

Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019

Lightweight Mitigation of Hardware Trojan Attacks in NoC-based Manycore Computing.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

HYDRA: Heterodyne Crosstalk Mitigation With Double Microring Resonators and Data Encoding for Photonic NoCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Minimizing Energy Costs for Geographically Distributed Heterogeneous Data Centers.

[BibT_eX]

[DOI]

Ninad Hogade

IEEE Trans. Sustain. Comput., 2018

Resilience-Aware Resource Management for Exascale Computing Systems.

[BibT_eX]

[DOI]

IEEE Trans. Sustain. Comput., 2018

Guest Editorial: Special Issue on Low-Power Dependable Computing.

[BibT_eX]

[DOI]

IEEE Trans. Sustain. Comput., 2018

BiGNoC: Accelerating Big Data Computing with Application-Specific Photonic Network-on-Chip Architectures.

[BibT_eX]

[DOI]

Dharanidhar Dang

Rabi N. Mahapatra

IEEE Trans. Parallel Distributed Syst., 2018

RAPID: Memory-Aware NoC for Latency Optimized GPGPU Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2018

LIBRA: Thermal and Process Variation Aware Reliability Management in Photonic Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2018

DyPhase: A Dynamic Phase Change Memory Architecture With Symmetric Write Latency and Restorable Endurance.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Rate-based thermal, power, and co-location aware resource management for heterogeneous data centers.

[BibT_eX]

[DOI]

Patrick J. Burns

Gregory A. Koenig

J. Parallel Distributed Comput., 2018

Mixed-criticality scheduling on heterogeneous multicore systems powered by energy harvesting.

[BibT_eX]

[DOI]

Integr., 2018

Advanced Driver-Assistance Systems: A Path Toward Autonomous Vehicles.

[BibT_eX]

[DOI]

IEEE Consumer Electron. Mag., 2018

Special session on overcoming reliability and energy-efficiency challenges with silicon photonics for future manycore computing.

[BibT_eX]

[DOI]

Davide Bertozzi

Hui Li

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Overcoming Energy and Reliability Challenges for IoT and Mobile Devices with Data Analytics.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

DAPPER: Data Aware Approximate NoC for GPGPU Architectures.

[BibT_eX]

[DOI]

Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Securing Photonic NoC Architectures from Hardware Trojans.

[BibT_eX]

[DOI]

Varun Bhat

Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Message from the HCW Program Committee Chair.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Introduction to HCW 2018.

[BibT_eX]

[DOI]

Alexey L. Lastovetsky

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

An Analysis of Multilevel Checkpoint Performance Models.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Mitigating the Energy Impacts of VBTI Aging in Photonic Networks-on-Chip Architectures with Multilevel Signaling.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

Cross-Layer Thermal Reliability Management in Silicon Photonic Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Adapting Convolutional Neural Networks for Indoor Localization with Smart Mobile Devices.

[BibT_eX]

[DOI]

Ayush Mittal

Saideep Tiku

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

PARM: power supply noise aware resource management for NoC based multicore systems in the dark silicon era.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures.

[BibT_eX]

[DOI]

Varun Bhat

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

A Runtime Framework for Robust Application Scheduling With Adaptive Parallelism in the Dark-Silicon Era.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-Based Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2017

Application of systems theoretic process analysis to a lane keeping assist system.

[BibT_eX]

[DOI]

Haneet Singh Mahajan

Thomas H. Bradley

Reliab. Eng. Syst. Saf., 2017

SWIFTNoC: A Reconfigurable Silicon-Photonic Network with Multicast-Enabled Channel Sharing for Multicore Architectures.

[BibT_eX]

[DOI]

Srinivas Desai

ACM J. Emerg. Technol. Comput. Syst., 2017

Indoor Localization with Smartphones: Harnessing the Sensor Suite in Your Pocket.

[BibT_eX]

[DOI]

Christopher Langlois

Saideep Tiku

IEEE Consumer Electron. Mag., 2017

DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

Energy-efficient and robust middleware prototyping for smart mobile computing.

[BibT_eX]

[DOI]

Saideep Tiku

Proceedings of the International Symposium on Rapid System Prototyping, 2017

Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling.

[BibT_eX]

[DOI]

Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

JAMS: Jitter-Aware Message Scheduling for FlexRay Automotive Networks.

[BibT_eX]

[DOI]

Vipin Kumar Kukkala

Thomas H. Bradley

Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Preemptive Resource Management for Dynamically Arriving Tasks in an Oversubscribed Heterogeneous Computing System.

[BibT_eX]

[DOI]

Dylan Machovec

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

An Analysis of Resilience Techniques for Exascale Computing Platforms.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Thermal-sensitive design and power optimization for a 3D torus-based optical NoC.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Optimizing checkpoint intervals for reduced energy use in exascale systems.

[BibT_eX]

[DOI]

Rohan Jhaveri

Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

DELCA: DVFS Efficient Low Cost Multicore Architecture.

[BibT_eX]

[DOI]

Shoumik Maiti

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Data analytics enables energy-efficiency and robustness: from mobile to manycores, datacenters, and networks (special session paper).

[BibT_eX]

[DOI]

Janardhan Rao Doppa

Krishnendu Chakrabarty

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

Islands of heaters: A novel thermal management framework for photonic NoCs.

[BibT_eX]

[DOI]

Dharanidhar Dang

Rabi N. Mahapatra

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

A System-Level Cosynthesis Framework for Power Delivery and On-Chip Data Networks in Application-Specific 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

HPC node performance and energy modeling with the co-location of applications.

[BibT_eX]

[DOI]

David A. Bader

J. Supercomput., 2016

Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

The Future of NoCs: New Technologies and Architectures.

[BibT_eX]

[DOI]

Partha Pratim Pande

Hiroki Matsutani

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

SPECTRA: A Framework for Thermal Reliability Management in Silicon-Photonic Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 18th System Level Interconnect Prediction Workshop, 2016

Run-time laser power management in photonic NoCs with on-chip semiconductor optical amplifiers.

[BibT_eX]

[DOI]

Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

Memory-aware circuit overlay NoCs for latency optimized GPGPU architectures.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Process variation aware crosstalk mitigation for DWDM based photonic NoC architectures.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Dynamic Resource Management for Parallel Tasks in an Oversubscribed Energy-Constrained Heterogeneous Environment.

[BibT_eX]

[DOI]

Dylan Machovec

Bhavesh Khemka

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

CHARM: A checkpoint-based resource management framework for reliable multicore computing in the dark silicon era.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Online Resource Management in Thermal and Energy Constrained Heterogeneous High Performance Computing.

[BibT_eX]

[DOI]

Patrick J. Burns

Proceedings of the 2016 IEEE 14th Intl Conf on Dependable, 2016

PICO: mitigating heterodyne crosstalk due to process variations and intermodulation effects in photonic NoCs.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Mitigation of homodyne crosstalk noise in silicon photonic NoC architectures with tunable decoupling.

[BibT_eX]

[DOI]

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

A Performance and Energy Comparison of Fault Tolerance Techniques for Exascale Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Computer and Information Technology, 2016

2015

Run-Time Management for Multicore Embedded Systems With Energy Harvesting.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Makespan and Energy Robust Stochastic Static Resource Allocation of a Bag-of-Tasks to a Heterogeneous Computing System.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2015

Soft and Hard Reliability-Aware Scheduling for Multicore Embedded Systems with Energy Harvesting.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2015

3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2015

Power and Thermal-Aware Workload Allocation in Heterogeneous Data Centers.

[BibT_eX]

[DOI]

Abdulla Al-Qawasmeh

IEEE Trans. Computers, 2015

Utility maximizing dynamic resource management in an oversubscribed energy-constrained heterogeneous computing system.

[BibT_eX]

[DOI]

Bhavesh Khemka

Ryan D. Friese

Sustain. Comput. Informatics Syst., 2015

A middleware framework for application-aware and user-specific energy optimization in smart mobile devices.

[BibT_eX]

[DOI]

Brad K. Donohoo

Chris Ohlsen

Pervasive Mob. Comput., 2015

3-D WiRED: A Novel WIDE I/O DRAM With Energy-Efficient 3-D Bank Organization.

[BibT_eX]

[DOI]

IEEE Des. Test, 2015

Crosstalk Mitigation for High-Radix and Low-Diameter Photonic NoC Architectures.

[BibT_eX]

[DOI]

IEEE Des. Test, 2015

Process variation aware dynamic power management in multicore systems with extended range voltage/frequency scaling.

[BibT_eX]

[DOI]

Shoumik Maiti

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Improving crosstalk resilience with wavelength spacing in photonic crossbar-based network-on-chip architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A Methodology for Co-Location Aware Application Performance Modeling in Multicore Computing.

[BibT_eX]

[DOI]

David A. Bader

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

A novel 3D graphics DRAM architecture for high-performance and low-energy memory accesses.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Integrated photonics in future multicore computing.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

Energy cost optimization for geographically distributed heterogeneous data centers.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Multicore Architectures.

[BibT_eX]

[DOI]

Srinivas Desai

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

VARSHA: variation and reliability-aware application scheduling with adaptive parallelism in the dark-silicon era.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

LearnLoc: A framework for smart indoor localization with embedded mobile devices.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

2014

Context-Aware Energy Enhancements for Smart Mobile Devices.

[BibT_eX]

[DOI]

IEEE Trans. Mob. Comput., 2014

METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

Silicon Nanophotonics for Future Multicore Architectures: Opportunities and Challenges.

[BibT_eX]

[DOI]

Yi Xu

IEEE Des. Test, 2014

NoC Scheduling for Improved Application-Aware and Memory-Aware Transfers in Multi-core Systems.

[BibT_eX]

[DOI]

Tejasi Pimpalkhute

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Process Variation Aware Synthesis of Application-Specific MPSoCs to Maximize Yield.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

An application-aware heterogeneous prioritization framework for NoC based chip multiprocessors.

[BibT_eX]

[DOI]

Tejasi Pimpalkhute

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

HELIX: Design and synthesis of hybrid nanophotonic application-specific network-on-chip architectures.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Utility Driven Dynamic Resource Management in an Oversubscribed Energy-Constrained Heterogeneous System.

[BibT_eX]

[DOI]

Bhavesh Khemka

Ryan D. Friese

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

PRATHAM: A power delivery-aware and thermal-aware mapping framework for parallel embedded applications on 3D MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Energy-aware resource management for computing systems.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on Contemporary Computing, 2014

Thermal, power, and co-location aware resource allocation in heterogeneous high performance computing systems.

[BibT_eX]

[DOI]

Gregory A. Koenig

Proceedings of the International Green Computing Conference, 2014

A hybrid framework for application allocation and scheduling in multicore systems with energy harvesting.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

HEFT: A hybrid system-level framework for enabling energy-efficient fault-tolerance in NoC based MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Fault-aware application scheduling in low-power embedded systems with energy harvesting.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

2013

Deadline and energy constrained dynamic resource allocation in a heterogeneous computing environment.

[BibT_eX]

[DOI]

J. Supercomput., 2013

MultiMaKe: Chip-multiprocessor driven memory-aware kernel pipelining.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

Energy and Deadline Constrained Robust Stochastic Static Resource Allocation.

[BibT_eX]

[DOI]

Proceedings of the Parallel Processing and Applied Mathematics, 2013

Reliability-aware and energy-efficient synthesis of NoC based MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

Thermal-aware semi-dynamic power management for multicore systems with energy harvesting.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

VERVE: A framework for variation-aware energy efficient synthesis of NoC-based MPSoCs with voltage islands.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

A co-synthesis methodology for power delivery and data interconnection networks in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

Harvesting-aware energy management for multicore platforms with hybrid energy storage.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands.

[BibT_eX]

[DOI]

Integr., 2012

Characterizing Vulnerability of Network Interfaces in Embedded Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2012

A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on VLSI Design, 2012

A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on VLSI Design, 2012

A Particle Swarm Optimization approach for synthesizing application-specific hybrid photonic networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Thermal-Aware Performance Optimization in Power Constrained Heterogenous Data Centers.

[BibT_eX]

[DOI]

Abdulla Al-Qawasmeh

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Exploiting spatiotemporal and device contexts for energy-efficient mobile embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

The roce-bush router: a case for routing-centric dimensional decomposition for low-latency 3D noC routers.

[BibT_eX]

[DOI]

Miguel Salas

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011

A Multi-Granularity Power Modeling Methodology for Embedded Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

A low overhead fault tolerant routing scheme for 3D Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

POSEIDON: A framework for application-specific Network-on-Chip synthesis for heterogeneous chip multiprocessors.

[BibT_eX]

[DOI]

Soohyun Kwon

Jeonghun Cho

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Energy-Constrained Dynamic Resource Allocation in a Heterogeneous Computing Environment.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Parallel Processing Workshops, 2011

Analysis of on-chip interconnection network interface reliability in multicore systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

AURA: An application and user interaction aware middleware framework for energy optimization in mobile devices.

[BibT_eX]

[DOI]

Brad K. Donohoo

Chris Ohlsen

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

NS-FTR: A fault tolerant routing scheme for networks on chip with permanent and runtime intermittent faults.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

OPAL: A multi-layer hybrid photonic NoC for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Stochastically robust static resource allocation for energy minimization with a makespan constraint in a heterogeneous computing environment.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE/ACS International Conference on Computer Systems and Applications, 2011

2010

CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

NARCO: Neighbor Aware Turn Model-Based Fault Tolerant Routing for NoCs.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2010

UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

OE+IOE: a novel turn model based fault tolerant routing scheme for networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009

System-level PVT variation-aware power exploration of on-chip communication architectures.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Cross-abstraction Functional Verification and Performance Analysis of Chip Multiprocessor Designs.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Informatics, 2009

Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A Methodology for Power-aware Pipelining via High-Level Performance Model Evaluations.

[BibT_eX]

[DOI]

Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009

Exploring serial vertical interconnects for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Fast exploration of bus-based communication architectures at the CCATB abstraction.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2008

Trends in Emerging On-Chip Interconnect Technologies.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2008

Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

System level performance analysis of carbon nanotube global interconnects for emerging chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors.

[BibT_eX]

[DOI]

Houman Homayoun

Mohammad A. Makhzan

Alexander V. Veidenbaum

Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008

Compiler driven data layout optimization for regular/irregular array access patterns.

[BibT_eX]

[DOI]

Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008

A framework for memory-aware multimedia application mapping on chip-multiprocessors.

[BibT_eX]

[DOI]

Luis Angel D. Bathen

Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008

Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency.

[BibT_eX]

[DOI]

Houman Homayoun

Mohammad A. Makhzan

Alexander V. Veidenbaum

Proceedings of the 45th Design Automation Conference, 2008

Methodology for multi-granularity embedded processor power model generation for an ESL design flow.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications.

[BibT_eX]

[DOI]

Chulho Shin

Peter Grun

Nizar Romdhane

Christopher K. Lennard

Des. Autom. Embed. Syst., 2007

Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

System level power estimation methodology with H.264 decoder prediction IP case study.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

2006

FABSYN: floorplan-aware bus architecture synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Formal performance evaluation of AMBA-based system-on-chip designs.

[BibT_eX]

[DOI]

Proceedings of the 6th ACM & IEEE International conference on Embedded software, 2006

COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

System-level power-performance trade-offs in bus matrix communication architecture synthesis.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Constraint-driven bus matrix synthesis for MPSoC.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Floorplan-aware automated synthesis of bus-based communication architectures.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Automated throughput-driven synthesis of bus-based communication architectures.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Using TLM for Exploring Bus-based SoC Communication Architectures.

[BibT_eX]

[DOI]

Nalini Venkatasubramanian

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

Dynamic Backlight Adaptation for Low-Power Handheld Devices.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2004

Extending the transaction level modeling approach for fast communication architecture exploration.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Fast exploration of bus-based on-chip communication architectures.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003

Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches.

[BibT_eX]

[DOI]