Sudeendra Kumar K
Orcid: 0000-0003-2513-8519
According to our database1,
Sudeendra Kumar K
authored at least 27 papers
between 2015 and 2023.
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Bibliography
2023
Lightweight Secured Split Test Technique with RMA Capability to Prevent IC Counterfeiting.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
2022
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
2019
Physical Unclonable Functions for On-Chip Instrumentation: Enhancing the Security of the Internal Joint Test Action Group Network.
IEEE Consumer Electron. Mag., 2019
2018
A novel configurable ring oscillator PUF with improved reliability using reduced supply voltage.
Microprocess. Microsystems, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Energy Efficient Ultra Low Power Solar Harvesting System Design with MPPT for IOT Edge Node Devices.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018
2017
Integr., 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Analysis of Side-Channel Attack AES Hardware Trojan Benchmarks against Countermeasures.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
2016
Implementation of MIMO data reordering and scheduling methodologies for eight-parallel variable length multi-path delay commutator FFT/IFFT.
IET Comput. Digit. Tech., 2016
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
2015
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Implementation of input data buffering and scheduling methodology for 8 parallel MDC FFT.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
An improved AES Hardware Trojan benchmark to validate Trojan detection schemes in an ASIC design flow.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015
A Novel PUF Based SST to Prevent Distribution of Rejected ICs from Untrusted Assembly.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015