Sudarshan Banerjee

According to our database1, Sudarshan Banerjee authored at least 18 papers between 1997 and 2010.

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Bibliography

2010
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures.
ACM Trans. Reconfigurable Technol. Syst., 2010

2009
Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Strip packing with precedence constraints and strip packing with release times.
Theor. Comput. Sci., 2009

2008
Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies.
ACM Trans. Embed. Comput. Syst., 2008

2007
Energy-aware co-processor selection for embedded processors on FPGAs.
Proceedings of the 25th International Conference on Computer Design, 2007

Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures.
Proceedings of the 44th Design Automation Conference, 2007

2006
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Minimizing peak power for application chains on architectures with partial dynamic reconfiguration.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement.
Proceedings of the 2005 Design, 2005

Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration.
Proceedings of the 42nd Design Automation Conference, 2005

2004
FIFO power optimization for on-chip networks.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Efficient search space exploration for HW-SW partitioning.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

1997
Parallel Algorithms for Finding the Most Vital Edge in Weighted Graphs.
J. Parallel Distributed Comput., 1997


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