Subramanian Rajagopalan

According to our database, Subramanian Rajagopalan authored at least 15 papers between 2000 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids.

Nitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala

Proceedings of the 28th International Conference on VLSI Design, 2015

2014

Fixing Double Patterning violations with look-ahead.

Sambuddha Bhattacharya, Subramanian Rajagopalan, Shabbir H. Batterywala

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Automatic design rule correction in presence of multiple grids and track patterns.

Nitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2009

Efficient Analog/RF Layout Closure with Compaction Based Legalization.

Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008

On Efficient and Robust Constraint Generation for Practical Layout Legalization.

Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Cell Swapping Based Migration Methodology for Analog and Custom Layouts.

Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

Impact of Modern Process Technologies on the Electrical Parameters of Interconnects.

Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A 3-dimensional FEM Based Resistance Extraction.

Subramanian Rajagopalan, Shabbir H. Batterywala

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal Processors.

Subramanian Rajagopalan, Sharad Malik

Proceedings of the Compiler Design Handbook: Optimizations and Machine Code Generation, 2007

2004

A formal concurrency model based architecture description language for synthesis of software development tools.

Wei Qin, Subramanian Rajagopalan, Sharad Malik

Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

2002

Design Tools for Application Specific Embedded Processors.

Wei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh

Proceedings of the Embedded Software, Second International Conference, 2002

Retargetable Very Long Instuction Word Compiler Framework for Digital Signal Processors.

Subramanian Rajagopalan, Sharad Malik

Proceedings of the Compiler Design Handbook: Optimizations and Machine Code Generation, 2002

2001

A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism.

Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Optimal Live Range Merge for Address Register Allocation in Embedded Programs.

Guilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik

Proceedings of the Compiler Construction, 10th International Conference, 2001

2000

Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints.

Subramanian Rajagopalan, Manish Vachharajani, Sharad Malik

Proceedings of the 2000 International Conference on Compilers, 2000