Subramanian Poothamkurissi Swaminathan

According to our database1, Subramanian Poothamkurissi Swaminathan authored at least 1 paper in 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2012
Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012


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