Subodh Gupta

According to our database, Subodh Gupta authored at least 9 papers between 1997 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2009

Clock power reduction for virtex-5 FPGAs.

Qiang Wang, Subodh Gupta, Jason Helge Anderson

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2007

CAD Techniques for Power Optimization in Virtex-5 FPGAs.

Subodh Gupta, Jason Helge Anderson, Linda Farragher, Qiang Wang

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2003

Energy and peak-current per-cycle estimation at RTL.

Subodh Gupta, Farid N. Najm

IEEE Trans. Very Large Scale Integr. Syst., 2003

2000

Bottom-Up High-Level Power Modeling and Estimation

Subodh Gupta

PhD thesis, 2000

Power modeling for high-level power estimation.

Subodh Gupta, Farid N. Najm

IEEE Trans. Very Large Scale Integr. Syst., 2000

Analytical models for RTL power estimation of combinational andsequential circuits.

Subodh Gupta, Farid N. Najm

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1999

Energy-per-cycle estimation at RTL.

Subodh Gupta, Farid N. Najm

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Power macro-models for DSP blocks with application to high-level synthesis.

Subodh Gupta, Farid N. Najm

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

1997

Power Macromodeling for High Level Power Estimation.

Subodh Gupta, Farid N. Najm

Proceedings of the 34st Conference on Design Automation, 1997