Subhendu Roy

According to our database, Subhendu Roy authored at least 17 papers between 2010 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

High-Speed Adder Design Space Exploration via Graph Neural Processes.

Hao Geng, Yuzhe Ma, Qi Xu, Jin Miao, Subhendu Roy, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021

Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory.

Urmimala Roy, Tanmoy Pramanik, Subhendu Roy, Avhishek Chatterjee, Leonard F. Register, Sanjay Kumar Banerjee

ACM Trans. Design Autom. Electr. Syst., 2021

2019

Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach.

Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018

SD-PUF: Spliced Digital Physical Unclonable Function.

Jin Miao, Meng Li, Subhendu Roy, Yuzhe Ma, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders.

Subhendu Roy, Yuzhe Ma, Jin Miao, Bei Yu

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2016

OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions.

Subhendu Roy, Derong Liu, Jagmohan Singh, Junhyung Um, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs.

Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Design for manufacturability and reliability in extreme-scaling VLSI.

Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, David Z. Pan

Sci. China Inf. Sci., 2016

LRR-DPUF: learning resilient and reliable digital physical unclonable function.

Jin Miao, Meng Li, Subhendu Roy, Bei Yu

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure.

Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction.

Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan, Deming Chen

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization.

Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions.

Subhendu Roy, Derong Liu, Junhyung Um, David Z. Pan

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures.

Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session).

Bei Yu, Subhendu Roy, Jhih-Rong Gao, David Z. Pan

CoRR, 2014

Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown.

Subhendu Roy, David Z. Pan

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2010

Large Scale VLSI Circuit Simulation Using Point Relaxation.

Subhendu Roy, Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar

Proceedings of the 2010 International Conference on Scientific Computing, 2010