Subhajit Das

Orcid: 0000-0001-9500-6656

Affiliations:
  • Indian Institute of Engineering Science and Technology, Howrah, India


According to our database1, Subhajit Das authored at least 22 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Squeeze Film Effect in Surface Micromachined Nano Ultrasonic Sensor for Different Diaphragm Displacement Profiles.
Sensors, 2023

Electrothermal modeling of Multilayer Graphene Nanoribbon (MLGNR) Interconnect considering Energy-per-Layer Screening.
Proceedings of the International Symposium on Devices, Circuits and Systems, 2023

Simulation-Based Switching Performance of Self-Heating Effect on SiC-based Power-Electronic Circuits.
Proceedings of the International Symposium on Devices, Circuits and Systems, 2023

2022
FPGA implementation of high-fidelity hybrid reversible watermarking algorithm.
Microprocess. Microsystems, March, 2022

Minimization of crosstalk noise and delay using reduced graphene nano ribbon (GNR) interconnect.
Microelectron. J., 2022

2021
Efficient FPGA implementation and verification of difference expansion based reversible watermarking with improved time and resource utilization.
Microprocess. Microsystems, 2021

A Brief Review of Recent Studies on Performance Improvement of Graphene Nanoribbon Interconnect.
Proceedings of the 4th International Symposium on Devices, Circuits and Systems, 2021

Modelling, Analysis and Optimization of a 4<sup>th</sup> Order Delta-Sigma ADC and its Non-Idealities for Audio Codec Applications Achieving Dynamic Range Above 100dB.
Proceedings of the 4th International Symposium on Devices, Circuits and Systems, 2021

Design of Two-Stage Fully-Differential Driver in SAR ADC with Indirect Feedback Compensation Technique.
Proceedings of the 4th International Symposium on Devices, Circuits and Systems, 2021

2020
Efficient FPGA implementation of corrected reversible contrast mapping algorithm for video watermarking.
Microprocess. Microsystems, 2020

Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D IC.
IET Comput. Digit. Tech., 2020

Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm for Reversible Invisible Watermarking.
IEEE Access, 2020

Design of a low power, high speed self calibrated dynamic latched comparator.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020

A Short Review on Graphene Nanoribbon Interconnect.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020

2019
Optimization of DC-DC Power Converter Design with Second Generation HiSIM_HV Model.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

Comparative Stability Analysis of Pristine and AsF5 Intercalation Doped Top Contact Graphene Nano Ribbon Interconnects.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

Estimation of non-linear effects for Capacitive DAC in SAR ADC: An Analytical Model.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

A low power driver amplifier for Fully Differential ADC.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

2018
VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach.
Circuits Syst. Signal Process., 2018

Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach.
Circuits Syst. Signal Process., 2018

2015
An adaptive feedback based reversible watermarking algorithm using difference expansion.
Proceedings of the 2nd IEEE International Conference on Recent Trends in Information Systems, 2015

2014
Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA.
Proceedings of the 2014 International Conference on Information Technology, 2014


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