Subash Chandar G.

According to our database, Subash Chandar G. authored at least 8 papers between 1999 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding.

Subash Chandar G., Mahesh Mehendale, R. Govindarajan

J. VLSI Signal Process., 2006

2005

Effective IP reuse for high quality SOC design.

Soujanna Sarkar, Subash Chandar G., Sanjay Shinde

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

An Effective IP Reuse Methodology for Quality System-on-Chip Design.

Soujanna Sarkar, Sanjay Shinde, Subash Chandar G.

Proceedings of the 2005 International Symposium on System-on-Chip, 2005

An Effective Framework for Enabling the Reuse of External Soft IP.

Soujanna Sarkar, Subash Chandar G.

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004

Reset Careabouts in a SoC Design.

Subrangshu Das, Subash Chandar G., Ashutosh Tiwari

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2001

Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers.

Subash Chandar G., S. Vaideeswaran

Proceedings of ASP-DAC 2001, 2001

2000

A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores.

Karthikeyan Madathil, Jagdish C. Rao, Subash Chandar G., Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999

A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology.

Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash Chandar G.

Proceedings of the IEEE International Conference On Computer Design, 1999