Su-Hon Lin

According to our database, Su-Hon Lin authored at least 11 papers between 2002 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

Efficient Reverse Converter Design for New Adaptable Four-Moduli Set {2^{<i>n</i> + <i>k</i>}, 2^<i>n</i> + 1, 2^<i>n</i> - 1, 2^2<i>n</i> + 1}.

Ming-Hwa Sheu, Yuan-Ching Kuo, Su-Hon Lin, Siang-Min Siao

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

2009

Efficient VLSI Design of a Reverse RNS Converter for New Flexible 4-Moduli Set (2^p+k, 2^p+1, 2^p-1, 2^2p+1).

Yuan-Ching Kuo, Su-Hon Lin, Ming-Hwa Sheu, Jia-You Wu, Peng-Siang Wang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

VLSI Design of Diminished-One Modulo 2ⁿ+1 Adder Using Circular Carry Selection.

Su-Hon Lin, Ming-Hwa Sheu

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2^<i>n</i>, 2^<i>n</i>+1 - 1, 2^<i>n</i> - 1).

Su-Hon Lin, Ming-Hwa Sheu, Chao-Hsiang Wang

IEICE Trans. Inf. Syst., 2008

Area-Time Efficient Modulo 2^<i>n</i> - 1 Adder Design Using Hybrid Carry Selection.

Su-Hon Lin, Ming-Hwa Sheu

IEICE Trans. Inf. Syst., 2008

Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2ⁿ, 2ⁿ⁺¹-1, 2ⁿ-1).

Su-Hon Lin, Ming-Hwa Sheu, Chao-Hsiang Wang, Yuan-Ching Kuo

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

Efficient VLSI Design of Modulo 2ⁿ-1 Adder Using Hybrid Carry Selection.

Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu, Si-Ying Chen

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

2006

Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1).

Su-Hon Lin, Ming-Hwa Sheu, Jing-Shiun Lin, Wen-Tsai Sheu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2004

An efficient VLSI design for a residue to binary converter for general balance moduli (2ⁿ-3, 2ⁿ+1, 2ⁿ-1, 2ⁿ+3).

Ming-Hwa Sheu, Su-Hon Lin, Chichyang Chen, Shyue-Wen Yang

IEEE Trans. Circuits Syst. II Express Briefs, 2004

2002

Fast compensative design approach for the approximate squaring function.

Ming-Hwa Sheu, Su-Hon Lin

IEEE J. Solid State Circuits, 2002

Fast design approach for implementing the approximate squaring function.

Ming-Hwa Sheu, Su-Hon Lin

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002