Stewart S. Taylor

According to our database, Stewart S. Taylor authored at least 16 papers between 1993 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2011

A flip-chip-packaged 1.8V 28dBm class-AB power amplifier with shielded concentric transformers in 32nm SoC CMOS.

Yulin Tan, Hongtao Xu, Mohammed A. El-Tanani, Stewart S. Taylor, Hasnain Lakdawala

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 2.5GHz 32nm 0.35mm² 3.5dB NF -5dBm P1dB fully differential CMOS push-pull LNA with integrated 34dBm T/R switch and ESD protection.

Chang-Tsung Fu, Hasnain Lakdawala, Stewart S. Taylor, Krishnamurthy Soumyanath

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Fully balanced low-noise transconductance amplifiers with P1dB > 0dBm in 45nm CMOS.

Hemasundar Mohan Geddada, José Silva-Martínez, Stewart S. Taylor

Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010

A 10 GHz low phase noise VCO employing current reuse and capacitive power combining.

Diptendu Ghosh, Stewart S. Taylor, Yulin Tan, Ranjit Gharpurey

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A Class-G Supply Modulator and Class-E PA in 130 nm CMOS.

Jeffrey S. Walling, Stewart S. Taylor, David J. Allstot

IEEE J. Solid State Circuits, 2009

A Fully Integrated Ultra-Low Insertion Loss T/R Switch for 802.11b/g/n Application in 90 nm CMOS Process.

Adil A. Kidwai, Chang-Tsung Fu, Jonathan C. Jensen, Stewart S. Taylor

IEEE J. Solid State Circuits, 2009

2008

A Broadband Low-Cost Direct-Conversion Receiver Front-End in 90 nm CMOS.

Jing-Hong Conan Zhan, Brent R. Carlton, Stewart S. Taylor

IEEE J. Solid State Circuits, 2008

2007

A 5 GHz, 21 dBm output-IP3 resistive feedback LNA in 90-nm CMOS.

Bevin G. Perumana, Jing-Hong Conan Zhan, Stewart S. Taylor, Joy Laskar

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006

A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process.

Yorgos Palaskas, Stewart S. Taylor, Stefano Pellerano, Ian A. Rippke, Ralph E. Bishop, Ashoke Ravi, Hasnain Lakdawala, Krishnamurthy Soumyanath

IEEE J. Solid State Circuits, 2006

A 5-GHz 108-Mb/s 2 $\times$2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm ${\rm P}_{\rm 1dB}$ Power Amplifiers in 90-nm CMOS.

Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, Brent R. Carlton, Mostafa A. Elmala, Ralph E. Bishop, Gaurab Banerjee, Rich B. Nicholls, Stanley K. Ling, Nati Dinur, Stewart S. Taylor, Krishnamurthy Soumyanath

IEEE J. Solid State Circuits, 2006

A 5GHz resistive-feedback CMOS LNA for low-cost multi-standard applications.

Jing-Hong Conan Zhan, Stewart S. Taylor

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 5GHz 108Mb/s 2x2 MIMO Transceiver with Fully Integrated +16dBm PAs in 90nm CMOS.

Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, Brent R. Carlton, Mostafa A. Elmala, Ralph E. Bishop, Gaurab Banerjee, Rich B. Nicholls, Stanley K. Ling, Stewart S. Taylor, Krishnamurthy Soumyanath

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction.

Yorgos Palaskas, Stewart S. Taylor, Stefano Pellerano, Ian A. Rippke, Ralph E. Bishop, Ashoke Ravi, Hasnain Lakdawala, Krishnamurthy Soumyanath

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

1997

A GaAs MESFET Schottky diode barrier height reference circuit.

Stewart S. Taylor

IEEE J. Solid State Circuits, 1997

1993

A high-performance GaAs pin electronics circuit for automatic test equipment.

Stewart S. Taylor

IEEE J. Solid State Circuits, October, 1993

A complete 400-Mb/s burst-mode data OEIC receiver.

I. Ross MacTaggart, Mark Bendett, Stewart S. Taylor

IEEE J. Solid State Circuits, October, 1993