Steven M. Nowick
Orcid: 0000-0002-8837-8109Affiliations:
- Columbia University, New York City, USA
According to our database1,
Steven M. Nowick
authored at least 100 papers
between 1989 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2009, "For contributions to asynchronous and mixed-timing integrated circuits and systems".
Timeline
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On csauthors.net:
Bibliography
2024
An Ultra-Low Cost and Multicast-Enabled Asynchronous NoC for Neuromorphic Edge Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024
2022
An Asynchronous Soft Macro for Ultra-Low Power Communication in Neuromorphic Computing.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Micro, 2021
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
2017
Achieving Lightweight Multicast in Asynchronous NoCs Using a Continuous-Time Multi-Way Read Buffer.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017
Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Networks-on-Chip.
Proceedings of the New Generation of CAS, 2017
An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017
A High-Throughput Asynchronous Multi-resource Arbiter Using a Pipelined Assignment Approach.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017
2016
Achieving lightweight multicast in asynchronous networks-on-chip using local speculation.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015
2014
A Flexible, Event-Driven Digital Filter With Frequency Response Independent of Input Sample Rate.
IEEE J. Solid State Circuits, 2014
Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
A low-latency asynchronous interconnection network with early arbitration resolution.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems.
Proceedings of the Design, Automation and Test in Europe, 2013
Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013
2012
Error-Correcting Unordered Codes and Hardware Support for Robust Asynchronous Global Communication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
ACM J. Emerg. Technol. Comput. Syst., 2011
A low-latency adaptive asynchronous interconnection network using bi-modal router nodes.
Proceedings of the NOCS 2011, 2011
A delay-insensitive bus-invert code and hardware support for robust asynchronous global communication.
Proceedings of the Design, Automation and Test in Europe, 2011
2010
An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz.
IEEE Trans. Very Large Scale Integr. Syst., 2010
ACM Trans. Design Autom. Electr. Syst., 2010
Proceedings of the 28th International Conference on Computer Design, 2010
An error-correcting unordered code and hardware support for robust asynchronous global communication.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication.
IEEE Trans. Very Large Scale Integr. Syst., 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008
Block-Level Relaxation for Timing-Robust Asynchronous Circuits Based on Eager Evaluation.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006
2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
A lattice-based framework for the classification and design of asynchronous pipelines.
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE J. Solid State Circuits, 2004
Proceedings of the 41th Design Automation Conference, 2004
2003
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003
Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003
2002
Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of the 2002 Design, 2002
2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Transformations for the Synthesis and Optimization of Asynchronous Distributed Control.
Proceedings of the 38th Design Automation Conference, 2001
Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols.
Proceedings of the 38th Design Automation Conference, 2001
Sequential optimization of asynchronous and synchronous fintie-state machines.
Springer, ISBN: 978-0-7923-7425-1, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000
1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces.
Proceedings of the 36th Conference on Design Automation, 1999
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998
1997
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997
1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
Proceedings of the 33st Conference on Design Automation, 1996
Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes.
Proceedings of the 33st Conference on Design Automation, 1996
1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
Symbolic hazard-free minimization and encoding of asynchronous finite state machines.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995
1994
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
1993
The design of a high-performance cache controller: a case study in asynchronous synthesis.
Integr., 1993
1992
Formal Methods Syst. Des., 1992
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991
1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989