Steven G. Walker

According to our database, Steven G. Walker authored at least 6 papers between 1999 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2007

An Integrated CAD Methodology for Evaluating MOSFET and Parasitic Extraction Models and Variability.

Koushik K. Das, Steven G. Walker, Manjul Bhushan

Proc. IEEE, 2007

2006

First-Order Incremental Block-Based Statistical Timing Analysis.

Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, Jeff Piaget, Natesan Venkateswaran, Jeffrey G. Hemmett

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2004

First-order incremental block-based statistical timing analysis.

Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan

Proceedings of the 41th Design Automation Conference, 2004

2001

Full-wave PEEC time-domain method for the modeling of on-chipinterconnects.

Phillip J. Restle, Albert E. Ruehli, Steven G. Walker, George Papadopoulos

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Multi-GHz interconnect effects in microprocessors.

Phillip J. Restle, Albert E. Ruehli, Steven G. Walker

Proceedings of the 2001 International Symposium on Physical Design, 2001

1999

Dealing with Inductance in High-Speed Chip Design.

Phillip J. Restle, Albert E. Ruehli, Steven G. Walker

Proceedings of the 36th Conference on Design Automation, 1999