Steven G. Dropsho

Affiliations:
  • University of Rochester, New York, USA


According to our database1, Steven G. Dropsho authored at least 20 papers between 2002 and 2011.

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Bibliography

2011
A phase adaptive cache hierarchy for SMT processors.
Microprocess. Microsystems, 2011

2010
Adaptive Cache Memories for SMT Processors.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Predicting replicated database scalability from standalone database profiling.
Proceedings of the 2009 EuroSys Conference, Nuremberg, Germany, April 1-3, 2009, 2009

2007
Miss Rate Prediction Across Program Inputs and Cache Configurations.
IEEE Trans. Computers, 2007

Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007

Tashkent+: memory-aware load balancing and update filtering in replicated databases.
Proceedings of the 2007 EuroSys Conference, Lisbon, Portugal, March 21-23, 2007, 2007

Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
Caching Dynamic Web Content: Designing and Analysing an Aspect-Oriented Solution.
Proceedings of the Middleware 2006, 2006

Tashkent: uniting durability with transaction ordering for high-performance scalable database replication.
Proceedings of the 2006 EuroSys Conference, Leuven, Belgium, April 18-21, 2006, 2006

2004
Dynamically Trading Frequency for Complexity in a GALS Microprocessor.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Dynamically reducing pressure on the physical register file through simple register sharing.
Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software, 2004

Hiding Synchronization Delays in a GALS Processor Microarchitecture.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

2003
Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor.
IEEE Micro, 2003

Dynamically Tuning Processor Resources with Adaptive Processing.
Computer, 2003

Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Dynamic Data Dependence Tracking and its Application to Branch Prediction.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

Miss Rate Prediction across All Program Inputs.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003

2002
Dynamic frequency and voltage control for a multiple clock domain microarchitecture.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Managing static leakage energy in microprocessor functional units.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002


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