Steven E. Raasch

According to our database1, Steven E. Raasch authored at least 13 papers between 2001 and 2023.

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Bibliography

2023

2019
Killi: Runtime Fault Classification to Deploy Low Voltage Caches without MBIST.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2018
Evaluating the Resilience of Parallel Applications.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

2017

Lifetime memory reliability data from the field.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant Multithreading.
Proceedings of the 54th Annual Design Automation Conference, 2017

On Characterizing Near-Threshold SRAM Failures in FinFET Technology.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Improving DRAM Fault Characterization through Machine Learning.
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2016

2015
A fast and accurate analytical technique to compute the AVF of sequential bits in a processor.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

2004
A scalable instruction queue design for exploiting parallelism.
PhD thesis, 2004

2003
The Impact of Resource Partitioning on SMT Processors.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003

2002
A Scalable Instruction Queue Design Using Dependence Chains.
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

2001
Integrating superscalar processor components to implement register caching.
Proceedings of the 15th international conference on Supercomputing, 2001


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