Steve B. Furber

Orcid: 0000-0002-6524-3367

Affiliations:
  • University of Manchester, School of Computer Science, UK


According to our database1, Steve B. Furber authored at least 217 papers between 1987 and 2024.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2005, "For contributions to the microarchitecture of embedded processor cores.".

Timeline

Legend:

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Links

Online presence:

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Bibliography

2024
FPGA-based fast bin-ratio spiking ensemble network for radioisotope identification.
Neural Networks, 2024

2023
BitBrain and Sparse Binary Coincidence (SBC) memories: Fast, robust learning and inference for neuromorphic architectures.
Frontiers Neuroinformatics, March, 2023

NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking.
CoRR, 2023

Unleashing the Potential of Spiking Neural Networks by Dynamic Confidence.
CoRR, 2023

A High-Throughput Low-Latency Interface Board for SpiNNaker-in-the-loop Real-Time Systems.
Proceedings of the 2023 International Conference on Neuromorphic Systems, 2023

2022
Event driven bio-inspired attentive system for the iCub humanoid robot on SpiNNaker.
Neuromorph. Comput. Eng., 2022

2022 roadmap on neuromorphic computing and engineering.
Neuromorph. Comput. Eng., 2022

Error driven synapse augmented neurogenesis.
Frontiers Artif. Intell., 2022

Instrumental Conditioning with Neuromodulated Plasticity on SpiNNaker.
Proceedings of the Neural Information Processing - 29th International Conference, 2022

Unsupervised STDP-based Radioisotope Identification Using Spiking Neural Networks Implemented on SpiNNaker.
Proceedings of the 8th International Conference on Event-Based Control, 2022

2021
Comparing Loihi with a SpiNNaker 2 prototype on low-latency keyword spotting and adaptive robotic control.
Neuromorph. Comput. Eng., 2021

Building Brains.
ERCIM News, 2021

The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing.
CoRR, 2021

An FPGA Implementation of Convolutional Spiking Neural Networks for Radioisotope Identification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Towards Biologically-Plausible Neuron Models and Firing Rates in High-Performance Deep Spiking Neural Networks.
Proceedings of the ICONS 2021: International Conference on Neuromorphic Systems 2021, 2021

2020
Low-Power Low-Latency Keyword Spotting and Adaptive Control with a SpiNNaker 2 Prototype and Comparison with Loihi.
CoRR, 2020

Spiking Associative Memory for Spatio-Temporal Patterns.
CoRR, 2020

spiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System.
IEEE Access, 2020

A GPS-Less Localization and Mobility Modelling (LMM) System for Wildlife Tracking.
IEEE Access, 2020

Robustness to Noisy Synaptic Weights in Spiking Neural Networks.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

Spiking Neural Network Based Low-Power Radioisotope Identification using FPGA.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Event-based Signal Processing for Radioisotope Identification.
Proceedings of the 6th International Conference on Event-Based Control, 2020

2019
Dynamic Power Management for Neuromorphic Many-Core Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Efficient Reward-Based Structural Plasticity on a SpiNNaker 2 Prototype.
IEEE Trans. Biomed. Circuits Syst., 2019

ATIS + SpiNNaker: a Fully Event-based Visual Tracking Demonstration.
CoRR, 2019

SpiNNaker 2: A 10 Million Core Processor System for Brain Simulation and Machine Learning.
CoRR, 2019

Real-Time Cortical Simulation on Neuromorphic Hardware.
CoRR, 2019

Stochastic rounding and reduced-precision fixed-point arithmetic for solving neural ODEs.
CoRR, 2019

SLAMBench 3.0: Systematic Automated Reproducible Evaluation of SLAM Systems for Robot Vision Challenges and Scene Understanding.
Proceedings of the International Conference on Robotics and Automation, 2019

2018
Behavioral Learning in a Cognitive Neuromorphic Robot: An Integrative Approach.
IEEE Trans. Neural Networks Learn. Syst., 2018

SpiNNaker: Event-Based Simulation - Quantitative Behavior.
IEEE Trans. Multi Scale Comput. Syst., 2018

Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application.
IEEE Trans. Biomed. Circuits Syst., 2018

Building a Spiking Neural Network Model of the Basal Ganglia on SpiNNaker.
IEEE Trans. Cogn. Dev. Syst., 2018

Visual attention and object naming in humanoid robots using a bio-inspired spiking neural network.
Robotics Auton. Syst., 2018

Navigating the Landscape for Real-Time Localization and Mapping for Robotics and Virtual and Augmented Reality.
Proc. IEEE, 2018

SpiNNTools: The Execution Engine for the SpiNNaker Platform.
CoRR, 2018

Navigating the Landscape for Real-time Localisation and Mapping for Robotics and Virtual and Augmented Reality.
CoRR, 2018

Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Deep Spiking Neural Network model for time-variant signals classification: a real-time speech recognition approach.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

SLAMBench2: Multi-Objective Head-to-Head Benchmarking for Visual SLAM.
Proceedings of the 2018 IEEE International Conference on Robotics and Automation, 2018

Network-on-chip evaluation for a novel neural architecture.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

2017
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems.
IEEE Trans. Biomed. Circuits Syst., 2017

Realising Turing's Dream.
Int. J. Unconv. Comput., 2017

Noisy Softplus: an activation function that enables SNNs to be trained as ANNs.
CoRR, 2017

Identifying Energy Holes in Randomly Deployed Hierarchical Wireless Sensor Networks.
IEEE Access, 2017

Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A fixed point exponential function accelerator for a neuromorphic many-core system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017


Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Optimized task graph mapping on a many-core neuromorphic supercomputer.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Parallel distribution of an inner hair cell and auditory nerve model for real-time application.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Brain-inspired computing.
IET Comput. Digit. Tech., 2016

Application-aware Retiming of Accelerators: A High-level Data-driven Approach.
CoRR, 2016

pyDVS: An extensible, real-time Dynamic Vision Sensor emulator using off-the-shelf hardware.
Proceedings of the 2016 IEEE Symposium Series on Computational Intelligence, 2016

Neuromorphic sampling on the SpiNNaker and parallella chip multiprocessors.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

High performance computing on SpiNNaker neuromorphic platform: A case study for energy efficient image processing.
Proceedings of the 35th IEEE International Performance Computing and Communications Conference, 2016

Efficient SpiNNaker simulation of a heteroassociative memory using the Neural Engineering Framework.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

Noisy Softplus: A Biology Inspired Activation Function.
Proceedings of the Neural Information Processing - 23rd International Conference, 2016

2015
SpiNNaker - Programming Model.
IEEE Trans. Computers, 2015

SpiNNaker: Enhanced multicast routing.
Parallel Comput., 2015

Accuracy and Efficiency in Fixed-Point Neural ODE Solvers.
Neural Comput., 2015

Reliable computation with unreliable computers.
IET Comput. Digit. Tech., 2015

Bio-Inspired Massively-Parallel Computation.
Proceedings of the Parallel Computing: On the Road to Exascale, 2015

Live demonstration: Handwritten digit recognition using spiking deep belief networks on SpiNNaker.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

ConvNets experiments on SpiNNaker.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Real-time event-driven spiking neural network object recognition on the SpiNNaker platform.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Live demonstration: Real-time event-driven object recognition on SpiNNaker.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Scalable energy-efficient, low-latency implementations of trained spiking Deep Belief Networks on SpiNNaker.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

An efficient SpiNNaker implementation of the Neural Engineering Framework.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM.
Proceedings of the IEEE International Conference on Robotics and Automation, 2015

Transport-Independent Protocols for Universal AER Communications.
Proceedings of the Neural Information Processing - 22nd International Conference, 2015

Markov Chain Monte Carlo inference on graphical models using event-based processing on the SpiNNaker neuromorphic architecture.
Proceedings of the 49th Annual Conference on Information Sciences and Systems, 2015

2014
The SpiNNaker Project.
Proc. IEEE, 2014

SpinNNaker: The world's biggest NoC.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Optimising the overall power usage on the SpiNNaker neuromimetic platform.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

Event-based neural computing on an autonomous mobile platform.
Proceedings of the 2014 IEEE International Conference on Robotics and Automation, 2014

Towards Real-World Neurorobotics: Integrated Neuromorphic Visual Attention.
Proceedings of the Neural Information Processing - 21st International Conference, 2014

On generating multicast routes for SpiNNaker.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

2013
Overview of the SpiNNaker System Architecture.
IEEE Trans. Computers, 2013

SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture.
Parallel Comput., 2013

SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation.
IEEE J. Solid State Circuits, 2013

Interconnection system for the spiNNaker biologically inspired multi-computer.
IET Comput. Digit. Tech., 2013

Algebraic approach to time borrowing.
IET Comput. Digit. Tech., 2013

Atomic computing - a different perspective on massively parallel problems.
Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013

Power analysis of large-scale, real-time neural networks on SpiNNaker.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

Correctness and performance of the SpiNNaker architecture.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

A location-independent direct link neuromorphic interface.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

Modeling populations of spiking neurons for fine timing sound localization.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

Spike-based learning of transfer functions with the SpiNNaker neuromimetic simulator.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

Real-Time Interface Board for Closed-Loop Robotic Tasks on the SpiNNaker Neural Computing System.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2013, 2013

Live demonstration: Ethernet communication linking two large-scale neuromorphic systems.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Modelling Word and Object Naming in Pure Alexia.
Proceedings of the 35th Annual Meeting of the Cognitive Science Society, 2013

Modelling Graded Semantic Effects in Lexical Decision.
Proceedings of the 35th Annual Meeting of the Cognitive Science Society, 2013

2012
A forecast-based STDP rule suitable for neuromorphic implementation.
Neural Networks, 2012

Scalable communications for a million-core neural processing architecture.
J. Parallel Distributed Comput., 2012

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System.
Int. J. Parallel Program., 2012

Event-driven MLP implementation on neuromimetic hardware.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

Visualising large-scale neural network models in real-time.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

Real time on-chip implementation of dynamical systems with spiking neurons.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

Population-based routing in the SpiNNaker neuromorphic architecture.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

A Real-Time, Event-Driven Neuromorphic System for Goal-Directed Attentional Selection.
Proceedings of the Neural Information Processing - 19th International Conference, 2012

Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Managing a Massively-Parallel Resource-Constrained Computing Architecture.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Generating Realistic Semantic Codes for Use in Neural Network Models.
Proceedings of the 34th Annual Meeting of the Cognitive Science Society, 2012

SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A hierachical configuration system for a massively parallel neural hardware platform.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

Live Demo: Spiking ratSLAM: Rat hippocampus cells in spiking neural hardware.
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012

An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

Large-Scale On-Chip Dynamic Programming Network Inferences Using Moderated Inter-core Communication.
Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012

2011
A Novel Programmable Parallel CRC Circuit.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric.
Parallel Comput., 2011

Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware.
Neural Networks, 2011

SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip.
ACM J. Emerg. Technol. Comput. Syst., 2011

SpiNNaker: Distributed Computer Engineering for Neuromorphics.
Proceedings of the Neural Nets WIRN11, 2011

Processing with a million cores.
Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

An event-driven model for the SpiNNaker virtual synaptic channel.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

Representing and decoding rank order codes using polychronization in a network of spiking neurons.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

A forecast-based biologically-plausible STDP learning rule.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

Event-Driven Simulation of Arbitrary Spiking Neural Networks on SpiNNaker.
Proceedings of the Neural Information Processing - 18th International Conference, 2011

Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis.
Proceedings of the Design, Automation and Test in Europe, 2011

Biologically-inspired massively-parallel architectures - Computing beyond a million processors.
Proceedings of the Design, Automation and Test in Europe, 2011

Maintaining real-time synchrony on SpiNNaker.
Proceedings of the 8th Conference on Computing Frontiers, 2011

Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Biologically inspired means for rank-order encoding images: a quantitative analysis.
IEEE Trans. Neural Networks, 2010

Modeling Spiking Neural Networks on SpiNNaker.
Comput. Sci. Eng., 2010

A Multicast Routing Scheme for a Universal Spiking Neural Network Architecture.
Comput. J., 2010

Interfacing Real-Time Spiking I/O with the SpiNNaker Neuromimetic Architecture.
Aust. J. Intell. Inf. Process. Syst., 2010

Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware.
Proceedings of the Ninth International Symposium on Parallel and Distributed Computing, 2010

The Leaky Integrate-and-Fire neuron: A platform for synaptic model exploration on the SpiNNaker chip.
Proceedings of the International Joint Conference on Neural Networks, 2010

Implementing spike-timing-dependent plasticity on SpiNNaker neuromorphic hardware.
Proceedings of the International Joint Conference on Neural Networks, 2010

Algorithm and software for simulation of spiking neural networks on the multi-chip SpiNNaker system.
Proceedings of the International Joint Conference on Neural Networks, 2010

A General-Purpose Model Translation System for a Universal Neural Chip.
Proceedings of the Neural Information Processing. Theory and Algorithms, 2010

Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system.
Proceedings of the 7th Conference on Computing Frontiers, 2010

SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network.
Proceedings of the 7th Conference on Computing Frontiers, 2010

Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker.
Proceedings of the 7th Conference on Computing Frontiers, 2010

A communication infrastructure for a million processor machine.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect.
Fundam. Informaticae, 2009

Adaptive admission control on the SpiNNaker MPSoC.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric.
Proceedings of the Eighth International Symposium on Parallel and Distributed Computing, 2009

Optimal connectivity in hardware-targetted MLP networks.
Proceedings of the International Joint Conference on Neural Networks, 2009

A universal abstract-time platform for real-time neural networks.
Proceedings of the International Joint Conference on Neural Networks, 2009

Evaluating rank-order code performance using a biologically-derived retinal model.
Proceedings of the International Joint Conference on Neural Networks, 2009

Understanding the interconnection network of SpiNNaker.
Proceedings of the 23rd international conference on Supercomputing, 2009

Implementing Learning on the SpiNNaker Universal Neural Chip Multiprocessor.
Proceedings of the Neural Information Processing, 16th International Conference, 2009

The Amulet chips: Architectural development for asynchronous microprocessors.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A Programmable Adaptive Router for a GALS Parallel System.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

Fault Tolerant Delay Insensitive Inter-chip Communication.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors.
Proceedings of the Ninth International Conference on Application of Concurrency to System Design, 2009

2008
Neural Systems Engineering.
Proceedings of the Computational Intelligence: A Compendium, 2008

The Future of Computer Technology and its Implications for the Computer Industry.
Comput. J., 2008

An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Virtual synaptic interconnect using an asynchronous network-on-chip.
Proceedings of the International Joint Conference on Neural Networks, 2008

SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor.
Proceedings of the International Joint Conference on Neural Networks, 2008

Efficient modelling of spiking neural networks on a scalable chip multiprocessor.
Proceedings of the International Joint Conference on Neural Networks, 2008

The Deferred Event Model for Hardware-Oriented Spiking Neural Networks.
Proceedings of the Advances in Neuro-Information Processing, 15th International Conference, 2008

SpiNNaker: The Design Automation Problem.
Proceedings of the Advances in Neuro-Information Processing, 15th International Conference, 2008

An admission control system for QoS provision on a best-effort GALS interconnect.
Proceedings of the 8th International Conference on Application of Concurrency to System Design (ACSD 2008), 2008

2007
Sparse Distributed Memory Using Rank-Order Neural Codes.
IEEE Trans. Neural Networks, 2007

A GALS Infrastructure for a Massively Parallel Multiprocessor.
IEEE Des. Test Comput., 2007

Maximising information recovery from rank-order codes.
Proceedings of the Data Mining, 2007

2006
An associative memory for the on-line recognition and prediction of temporal sequences
CoRR, 2006

The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

On-chip and inter-chip networks for modeling large-scale neural systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Living with Failure: Lessons from Nature?
Proceedings of the 11th European Test Symposium, 2006

2005
A System for Transmitting a Coherent Burst of Activity Through a Network of Spiking Neurons.
Proceedings of the Neural Nets, 16th Italian Workshop on Neural Nets, 2005

The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics.
Proceedings of the Integrated Circuit and System Design, 2005

A Low Power Embedded Dataflow Coprocessor.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Future Trends in SoC Interconnect.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

A Spiking Neural Sparse Distributed Memory Implementation for Learning and Predicting Temporal Sequences.
Proceedings of the Artificial Neural Networks: Biological Inspirations, 2005

2004
Design and Analysis of a Self-Timed Duplex Communication System.
IEEE Trans. Computers, 2004

Sparse distributed memory using <i>N</i>-of-<i>M</i> codes.
Neural Networks, 2004

An asynchronous on-chip network router with quality-of-service (QoS) support.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Minimizing the Power Consumption of an Asynchronous Multiplier.
Proceedings of the Integrated Circuit and System Design, 2004

The design of a low power asynchronous multiplier.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip.
Proceedings of the 2004 Design, 2004

2003
An asynchronous ternary logic signaling system.
IEEE Trans. Very Large Scale Integr. Syst., 2003

An asynchronous copy-back cache architecture.
Microprocess. Microsystems, 2003

Editorial.
Microprocess. Microsystems, 2003

An Investigation into the Security of Self-Timed Circuits.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

2002
Chain: A Delay-Insensitive Chip Area Interconnect.
IEEE Micro, 2002

Validating the AMULET Microprocessors.
Comput. J., 2002

An Asynchronous Victim Cache.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

2001
Power Management in the Amulet Microprocessors.
IEEE Des. Test Comput., 2001

A Low-Power Self-Timed Viterbi Decoder.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

2000
MARBLE: an asynchronous on-chip macrocell bus.
Microprocess. Microsystems, 2000

AMULET3: A 100 MIPS Asynchronous Embedded Processor.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

AMULET3i - An Asynchronous System-on-Chip.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1999
AMULET2e: an asynchronous embedded controller.
Proc. IEEE, 1999

AMULET3 Revealed.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1998
Asynchronous Embedded Control.
Integr. Comput. Aided Eng., 1998

AMULET3: a high-performance self-timed ARM microprocessor.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language.
Proceedings of the 12<sup>th</sup> European Simulation Multiconference - Simulation, 1998

The Design of an Asynchronous VHDL Synthesizer.
Proceedings of the 1998 Design, 1998

Asynchronous Macrocell Interconnect using MARBLE.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1997
AMULET1: A Asynchronous ARM Microprocessor.
IEEE Trans. Computers, 1997

Built-In Self-Testing of Micropipelines.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

AMULET2e: An Asynchronous Embedded Controller.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

1996
Four-phase micropipeline latch control circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1996

The Return of Asynchronous Logic.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Dynamic logic in four-phase micropipelines.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

1995
Scan testing of micropipelines.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Scan testing of asynchronous sequential circuits.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

1994
The Design and Evaluation of an Asynchronous Microprocessor.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

AMULET1: A Micropipelined ARM.
Proceedings of the Spring COMPCON 94, Digest of Papers, San Francisco, California, USA, February 28, 1994

1993
A micropipelined ARM.
Proceedings of the VLSI 93, 1993

1992
RISC architectures : Heudin, J C and Panetto, C Chapman & Hall, London, UK (1992) ISBN 0 412 45340 1, £19.95, pp 261.
Microprocess. Microsystems, 1992

Register Locking in an Asynchronous Microprocessor.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1990
Useful RISC text from ARM development team leader.
Microprocess. Microsystems, 1990

ARM3 - a study in design for compatibility.
Microprocess. Microsystems, 1990

1987
RISC architecture: D Tabak Research Studies Press, Letchworth, UK (1987) £19.95 pp 175.
Microprocess. Microsystems, 1987


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