Stephen V. Kosonocky

According to our database, Stephen V. Kosonocky authored at least 41 papers between 1995 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Predict; Don't React for Enabling Efficient Fine-Grain DVFS in GPUs.

Srikant Bharadwaj, Shomit Das, Kaushik Mazumdar, Bradford M. Beckmann, Stephen Kosonocky

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022

Predict; Do not React for Enabling Efficient Fine Grain DVFS in GPUs.

Srikant Bharadwaj, Shomit Das, Kaushik Mazumdar, Bradford M. Beckmann, Stephen Kosonocky

CoRR, 2022

2021

A New Era of Tailored Computing.

Mark Papermaster, Stephen Kosonocky, Gabriel H. Loh, Samuel Naffziger

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2018

Zen: An Energy-Efficient High-Performance × 86 Core.

Teja Singh, Alex Schaefer, Sundar Rangarajan, Deepesh John, Carson Henrion, Russell Schreiber, Miguel Rodriguez, Stephen Kosonocky, Samuel Naffziger, Amy Novak

IEEE J. Solid State Circuits, 2018

2017

Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management.

Sriram Sundaram, Aaron Grenat, Samuel Naffziger, Tom Burd, Stephen Kosonocky, Steven Liepe, Ravinder Rachala, Miguel Rodriguez, Michael Austin, Sriram Sambamurthy

IEEE J. Solid State Circuits, 2017

3.2 Zen: A next-generation high-performance ×86 core.

Teja Singh, Sundar Rangarajan, Deepesh John, Carson Henrion, Shane Southard, Hugh McIntyre, Amy Novak, Stephen Kosonocky, Ravi Jotwani, Alex Schaefer, Edward Chang, Joshua Bell, Michael Co

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU.

Sriram Sundaram, Sriram Sambamurthy, Michael Austin, Aaron Grenat, Michael Golden, Stephen Kosonocky, Samuel Naffziger

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management.

Aaron Grenat, Sriram Sundaram, Stephen Kosonocky, Ravinder Rachala, Sriram Sambamurthy, Steven Liepe, Miguel Rodriguez, Tom Burd, Adam Clark, Michael Austin, Samuel Naffziger

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Modeling and implementation of a fully-digital integrated per-core voltage regulation system in a 28nm high performance 64-bit processor.

Ravinder Rachala, Miguel Rodriguez, Stephen Kosonocky, Milos Trajkovic

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

2015

Steamroller Module and Adaptive Clocking System in 28 nm CMOS.

Kathryn Wilcox, Robert Cole, Harry R. Fair III, Kevin Gillespie, Aaron Grenat, Carson Henrion, Ravi Jotwani, Stephen Kosonocky, Benjamin Munger, Samuel Naffziger, Robert S. Orefice, Sanjay Pant, Donald A. Priore, Ravinder Rachala, Jonathan White

IEEE J. Solid State Circuits, 2015

Highlights of the IEEE ISSCC 2014 Processors, Digital, Memory, Biomedical & Next-Generation Systems Technologies, and Imagers, MEMS, Medical & Displays Sessions.

Vivek De, Stephen Kosonocky, Jonathan Chang, Yogesh K. Ramadass, David Stoppa

IEEE J. Solid State Circuits, 2015

2014

5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS.

Kevin Gillespie, Harry R. Fair III, Carson Henrion, Ravi Jotwani, Stephen V. Kosonocky, Robert S. Orefice, Donald A. Priore, Jonathan White, Kathryn Wilcox

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012

Power/performance optimization of many-core processor SoCs.

Stephen Kosonocky, Vladimir Stojanovic, Kees van Berkel, Ming-Yang Chao, Tobias Knoll, Joshua Friedrich

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs.

Kyle Craig, Yousef Shakhsheer, Sudhanshu Khanna, Saad Arrabi, John C. Lach, Benton H. Calhoun, Stephen Kosonocky

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

2011

An x86-64 Core in 32 nm SOI CMOS.

Ravi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, Amy Novak, Sam Naffziger

IEEE J. Solid State Circuits, 2011

Practical power gating and dynamic voltage/frequency scaling.

Stephen Kosonocky

Proceedings of the 2011 IEEE Hot Chips 23 Symposium (HCS), 2011

2010

Are you having fun yet?

Stephen V. Kosonocky

IEEE Des. Test Comput., 2010

An x86-64 core implemented in 32nm SOI CMOS.

Ravi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, Greg Constant, Amy Novak, Sam Naffziger

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing.

Azeez J. Bhavnagarwala, Stephen Kosonocky, Carl Radens, Yuen H. Chan, Kevin Stawiasz, Uma Srinivasan, Steven P. Kowalczyk, Matthew M. Ziegler

IEEE J. Solid State Circuits, 2008

Keeping hot chips cool: are IC thermal problems hot air?

Ruchir Puri, Devadas Varma, Darvin Edwards, Alan J. Weger, Paul D. Franzon, Andrew Yang, Stephen V. Kosonocky

Proceedings of the 45th Design Automation Conference, 2008

2007

A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs.

Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz, Marios C. Papaefthymiou

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Introduction to the Special Issue on the 2006 Symposium on VLSI Circuits.

Stephen V. Kosonocky, Kazuo Yano

IEEE J. Solid State Circuits, 2007

Multi-Dimensional Circuit and Micro-Architecture Level Optimization.

Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Structured and tuned array generation (STAG) for high-performance random logic.

Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Early Power-Aware Design & Validation: Myth or Reality?

Gila Kamhi, Sarah Miller, Stephen Bailey Mentor, Wolfgang Nebel, Y. C. Wong, Juergen Karmann, Enrico Macii, Stephen V. Kosonocky, Steve Curtis

Proceedings of the 44th Design Automation Conference, 2007

2005

Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies.

Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky

Integr., 2005

2004

A synchronous interface for SoCs with multiple clock domains.

Visvesh S. Sathe, Conrad H. Ziesler, Marios C. Papaefthymiou, Suhwan Kim, Stephen V. Kosonocky

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Experimental measurement of a novel power gating structure with intermediate power saving mode.

Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Characterization of logic circuit techniques for high leakage CMOS technologies.

Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits.

Jean-Olivier Plouchart, Noah Zamdmer, Jonghae Kim, Melanie Sherony, Yue Tan, Asit Ray, Mohamed Talbi, Lawrence F. Wagner, Kun Wu, Naftali E. Lustig, Shreesh Narasimha, Patricia O'Neil, Nghia Phan, Michael Rohn, James Strom, David M. Friend, Stephen V. Kosonocky, Daniel R. Knebel, Suhwan Kim, Keith A. Jenkins, Michel M. Rivier

IBM J. Res. Dev., 2003

Low-power circuits and technology for wireless digital systems.

Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban

IBM J. Res. Dev., 2003

Understanding and minimizing ground bounce during mode transition of power gating structures.

Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Minimizing inductive noise in system-on-a-chip with multiple power gating structures.

Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz, David F. Heidel, Michael Immediato

Proceedings of the ESSCIRC 2003, 2003

2002

Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits.

Alice Wang, Anantha P. Chandrakasan, Stephen V. Kosonocky

Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Low power integrated scan-retention mechanism.

Victor V. Zyuban, Stephen V. Kosonocky

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

2001

Enchanced multi-threshold (MTCMOS) circuits using variable well bias.

Stephen V. Kosonocky, Michael Immediato, Peter E. Cottrell, Terence B. Hook, Randy W. Mann, Jeff Brown

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design.

W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Interconnect-centric Array Architectures for Minimum SRAM Access Time.

Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

1998

Designing a Testable System on a Chip.

Stephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Benjamin D. Parker, T. V. Rajeevakumar, Kevin Stawiasz

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

An eight-issue tree-VLIW processor for dynamic binary translation.

Kemal Ebcioglu, Jason Fritts, Stephen Kosonocky, Michael Gschwind, Erik R. Altman, Krishnan Kailas, Terry Bright

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1995

A continuous density neural tree network word spotting system.

Stephen V. Kosonocky, Richard J. Mammone

Proceedings of the 1995 International Conference on Acoustics, 1995