Stephen Sunter

According to our database, Stephen Sunter authored at least 18 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2024

A Method for Simulating Mixed-Signal ATE Tests.

Stephen Sunter, Vladimir Zivkovic, Bartlomiej Praselski

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

Digital Scan and ATPG for Analog Circuits.

Stephen Sunter, Krzysztof Jurga

Proceedings of the IEEE International Test Conference, 2024

2021

Automated Observability Analysis for Mixed-Signal Circuits.

Stephen Sunter, Krzysztof Jurga

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

2020

Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs.

Stephen Sunter, Michal Wolinski, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Nektar Xama, Jhon Gomez, Georges G. E. Gielen

Proceedings of the IEEE International Test Conference, 2020

Analog Fault Simulation - a Hot Topic!

Stephen Sunter

Proceedings of the IEEE European Test Symposium, 2020

2019

Efficient Analog Defect Simulation.

Stephen Sunter

Proceedings of the IEEE International Test Conference, 2019

2018

IP session on ISO26262 EDA.

Art Schaldenbrand, Yervant Zorian, Stephen Sunter, Peter Sarson

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Measuring mixed-signal test stimulus quality.

Krzysztof Jurga, Stephen Sunter

Proceedings of the 23rd IEEE European Test Symposium, 2018

2017

A/MS benchmark circuits for comparing fault simulation, DFT, and test generation methods.

Stephen Sunter, Peter Sarson

Proceedings of the IEEE International Test Conference, 2017

2016

Using Mixed-Signal Defect Simulation to Close the Loop Between Design and Test.

Stephen Sunter, Krzysztof Jurga, Andrew Laidler

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Automated measurement of defect tolerance in mixed-signal ICs.

Stephen Sunter, Alessandro Valerio, Riccardo Miglierina

Proceedings of the 2016 IEEE International Test Conference, 2016

Closing the loop between analog design and test.

Stephen Sunter

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Measuring defect tolerance within mixed-signal ICs.

Stephen Sunter, Alessandro Valerio, Riccardo Miglierina

Proceedings of the 21th IEEE European Test Symposium, 2016

2015

Special session: Hot topics: Statistical test methods.

Manuel J. Barragán, Gildas Léger, Florence Azaïs, Ronald D. Blanton, Adit D. Singh, Stephen Sunter

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

2014

Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics.

Haralampos-G. D. Stratigopoulos, Stephen Sunter

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Efficient Monte Carlo-based analog parametric fault modelling.

Haralampos-G. D. Stratigopoulos, Stephen Sunter

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Fast BIST of I/O Pin AC specifications and inter-chip delays.

Stephen Sunter, Saghir A. Shaikh, Qing Lin

Proceedings of the 2014 International Test Conference, 2014

Practical random sampling of potential defects for analog fault simulation.

Stephen Sunter, Krzysztof Jurga, Peter Dingenen, Ronny Vanhooren

Proceedings of the 2014 International Test Conference, 2014