Stephen Richardson

Orcid: 0000-0003-4359-3638

According to our database1, Stephen Richardson authored at least 29 papers between 1989 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
IEEE J. Solid State Circuits, March, 2024

2023
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains.
ACM Trans. Reconfigurable Technol. Syst., June, 2023

AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.
ACM Trans. Embed. Comput. Syst., March, 2023

2022
Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022


Visualizing Tacit Knowledge in Cardiac Operating Room: A Need-Finding Study.
Proceedings of the Design, User Experience, and Usability: Design for Emotion, Well-being and Health, Learning, and Culture, 2022

2020
A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020


2017
Programming Heterogeneous Systems from an Image Processing DSL.
ACM Trans. Archit. Code Optim., 2017

Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era.
IEEE Des. Test, 2017

2016
A Systematic Approach to Blocking Convolutional Neural Networks.
CoRR, 2016

Evaluating programmable architectures for imaging and vision applications.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Improving energy efficiency of DRAM by exploiting half page row access.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

2015
Building Conflict-Free FFT Schedules.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2013
An area-efficient minimum-time FFT schedule using single-ported memory.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

2012
Bringing up a chip on the cheap.
IEEE Des. Test, 2012

Avoiding game over: bringing design to the next level.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Removing overhead from high-level interfaces.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Understanding sources of ineffciency in general-purpose chips.
Commun. ACM, 2011

Intermediate representations for controllers in chip generators.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Rethinking Digital Design: Why Design Must Change.
IEEE Micro, 2010

Understanding sources of inefficiency in general-purpose chips.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009
Using a configurable processor generator for computer architecture prototyping.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

A memory system design framework: creating smart memories.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

2008
Verification of chip multiprocessor memory systems using a relaxed scoreboard.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

1993
The Experience of Developing a Large-Scale Natural Language Processing System: Critique.
Proceedings of the Natural Language Processing: The PLNLP Approach, 1993

1989
Interprocedural Optimization: Experimental Results.
Softw. Pract. Exp., 1989

Interprocedural analysis vs. procedure integration.
Inf. Process. Lett., 1989

Code Optimization Across Procedures.
Computer, 1989


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