Stephen Pateras

According to our database1, Stephen Pateras authored at least 11 papers between 1988 and 2004.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

1988
1990
1992
1994
1996
1998
2000
2002
2004
0
1
2
3
1
1
1
1
1
1
1
1
2
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2004
Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having Both.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
Achieving At-Speed Structural Test.
IEEE Des. Test Comput., 2003

2002
IP for Embedded Diagnosis.
IEEE Des. Test Comput., 2002

Embedded Diagnosis IP.
Proceedings of the 2002 Design, 2002

2000
Bridging the gap between embedded test and ATE.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
An embedded technique for at-speed interconnect testing.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1997
Advanced microprocessor test strategy and methodology.
IBM J. Res. Dev., 1997

1995
Avoiding Unknown States When Scanning Mutually Exclusive Latches.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1991
Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits.
Proceedings of the 28th Design Automation Conference, 1991

1988
A self-reconfiguration scheme for fault-tolerant VLSI processor arrays.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988


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