Stephen O'Kane

According to our database1, Stephen O'Kane authored at least 6 papers between 2004 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2007
An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006
A Study of Shared Buffer Memory Segmentation for Packet Switched Networks.
Proceedings of the Advanced International Conference on Telecommunications and International Conference on Internet and Web Applications and Services (AICT/ICIW 2006), 2006

2005
Design and implementation of a shared buffer architecture for a gigabit Ethernet packet switch.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

The Design and Implementation of a Shared Packet Buffer Architecture for Fixed and Variable Sized Packets.
Proceedings of the Telecommunications 2005: Advanced Industrial Conference on Telecommunications / Service Assurance with Partial and Intermittent Resources Conference / E-Learning on Telecommunications Workshop (AICT / SAPIR / ELETE 2005), 2005

Implementing High Speed IP Address Lookups in Hardware.
Proceedings of the Telecommunications 2005: Advanced Industrial Conference on Telecommunications / Service Assurance with Partial and Intermittent Resources Conference / E-Learning on Telecommunications Workshop (AICT / SAPIR / ELETE 2005), 2005

2004
An investigation into the design of high-performance shared buffer architectures based on FPGA technology with embedded memory.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004


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