Stephen Nease

According to our database1, Stephen Nease authored at least 14 papers between 2012 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
A Programmable and Configurable Mixed-Mode FPAA SoC.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Learning in Silicon Beyond STDP: A Neuromorphic Implementation of Multi-Factor Synaptic Plasticity With Calcium-Based Dynamics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Floating-gate-based intrinsic plasticity with low-voltage rate control.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

SoC FPAA IC, PCB, and tool demonstration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Transforming mixed-signal circuits class through SoC FPAA IC, PCB, and toolset.
Proceedings of the 11th European Workshop on Microelectronics Education, 2016

2015
Neural and analog computation on reconfigurable mixed-signal platforms.
PhD thesis, 2015

Power-efficient estimation of silicon neuron firing rates with floating-gate transistors.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Device mismatch in a neuromorphic system implements random features for regression.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2013
A Learning-Enabled Neuron Array IC Based Upon Transistor Channel Models of Biological Phenomena.
IEEE Trans. Biomed. Circuits Syst., 2013

Computing with networks of spiking neurons on a biophysically motivated floating-gate based neuromorphic integrated circuit.
Neural Networks, 2013

STDP-enabled learning on a reconfigurable neuromorphic platform.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012
Modeling and Implementation of Voltage-Mode CMOS Dendrites on a Reconfigurable Analog Platform.
IEEE Trans. Biomed. Circuits Syst., 2012

A Digitally Enhanced Dynamically Reconfigurable Analog Platform for Low-Power Signal Processing.
IEEE J. Solid State Circuits, 2012

A mixed-mode FPAA SoC for analog-enhanced signal processing.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012


  Loading...