Stephen M. Plaza

Affiliations:
  • Howard Hughes Medical Institute, Janelia Research Campus, Ashburn, USA


According to our database1, Stephen M. Plaza authored at least 27 papers between 2005 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2022
neuPrint: An open access tool for EM connectomics.
Frontiers Neuroinformatics, 2022

2021
CONFIRMS: A Toolkit for Scalable, Black Box Connectome Assessment and Investigation.
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021

2020
Latent Feature Representation via Unsupervised Learning for Pattern Discovery in Massive Electron Microscopy Image Volumes.
CoRR, 2020

2016
Large-Scale Electron Microscopy Image Segmentation in Spark.
CoRR, 2016

Fully-Automatic Synapse Prediction and Validation on a Large Data Set.
CoRR, 2016

Focused Proofreading to Reconstruct Neural Connectomes from EM Images at Scale.
Proceedings of the Deep Learning and Data Labeling for Medical Applications, 2016

2015
Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014
Graph-based active learning of agglomeration (GALA): a Python library to segment 2D and 3D neuroimages.
Frontiers Neuroinformatics, 2014

Automatic Neuron Type Identification by Neurite Localization in the Drosophila Medulla.
CoRR, 2014

Annotating Synapses in Large EM Datasets.
CoRR, 2014

Focused Proofreading: Efficiently Extracting Connectomes from Segmented EM Images.
CoRR, 2014

Small Sample Learning of Superpixel Classifiers for EM Segmentation- Extended Version.
CoRR, 2014

A Context-aware Delayed Agglomeration Framework for EM Segmentation.
CoRR, 2014

Identifying Synapses Using Deep and Wide Multiscale Recursive Networks.
CoRR, 2014

Small Sample Learning of Superpixel Classifiers for EM Segmentation.
Proceedings of the Medical Image Computing and Computer-Assisted Intervention - MICCAI 2014, 2014

Protecting integrated circuits from piracy with test-aware logic locking.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2011
Multi-mode redundancy removal.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2009
Signature-Based SER Analysis and Design of Logic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2008
Synthesis and Verification of Digital Circuits using Functional Simulation and Boolean Satisfiability.
PhD thesis, 2008

Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Optimizing non-monotonic interconnect using functional simulation and logic restructuring.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Random Stimulus Generation using Entropy and XOR Constraints.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Architecting a reliable CMP switch architecture.
ACM Trans. Archit. Code Optim., 2007

Enhancing design robustness with reliability-aware resynthesis and logic simulation.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Node Mergers in the Presence of Don't Cares.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
BulletProof: a defect-tolerant CMP switch architecture.
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

2005
STACCATO: disjoint support decompositions from BDDs through symbolic kernels.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005


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